diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 5a15365..9e76a4a 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -18,7 +18,7 @@
 #include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
 #endif
 
 /*
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index aca7793..c882bd3 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -95,7 +95,7 @@
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index d96406f..17bd53d 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
 static inline u32 read_cntfrq(void)
 {
 	u32 frq;
@@ -29,8 +29,8 @@
 	gd->arch.tbl = 0;
 	gd->arch.tbu = 0;
 
-#ifdef CONFIG_SYS_HZ_CLOCK
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = read_cntfrq();
 #endif
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d09c21d..25e4b49 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -313,9 +313,9 @@
 
 int arch_cpu_init(void)
 {
-	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
-		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+		(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
 	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 0e7d5fa..599b7e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -183,7 +183,7 @@
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
-					    CONFIG_SYS_IFC_ADDR);
+					    CFG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 954fa5f..dbb0766 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -42,7 +42,7 @@
 
 static void __secure ls1_fsm_setup(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
 
 	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@
 
 static void __secure ls1_start_fsm(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 67764cc..f7cc457 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -18,7 +18,7 @@
 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
 
 #define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION	(CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,7 +67,7 @@
 {
 	ulong tmo;
 	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
 	ulong rndoff;
 
 	rndoff = (usec % 10) ? 1 : 0;
diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c
index 556eaf8..c30af4f 100644
--- a/arch/arm/cpu/armv7m/systick-timer.c
+++ b/arch/arm/cpu/armv7m/systick-timer.c
@@ -18,7 +18,7 @@
  * The number of reference clock ticks that correspond to 10ms is normally
  * defined in the SysTick Calibration register's TENMS field. However, on some
  * devices this is wrong, so this driver allows the clock rate to be defined
- * using CONFIG_SYS_HZ_CLOCK.
+ * using CFG_SYS_HZ_CLOCK.
  */
 
 #include <common.h>
@@ -76,10 +76,10 @@
 
 	/*
 	 * If the TENMS field is inexact or wrong, specify the clock rate using
-	 * CONFIG_SYS_HZ_CLOCK.
+	 * CFG_SYS_HZ_CLOCK.
 	 */
-#if defined(CONFIG_SYS_HZ_CLOCK)
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#if defined(CFG_SYS_HZ_CLOCK)
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bbaa91f..99413ef 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -114,7 +114,7 @@
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -130,9 +130,9 @@
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #ifdef CONFIG_FSL_IFC
-	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+	/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+	  CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
@@ -391,7 +391,7 @@
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	{},	/* space holder for secure mem */
 #endif
 	{},
@@ -445,7 +445,7 @@
 	if (el == 3)
 		gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
 	else
-		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
+		gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
@@ -568,7 +568,7 @@
 		}
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		if (el == 3) {
 			/*
@@ -580,7 +580,7 @@
 			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 			final_map[index].virt = gd->arch.secure_ram & ~0x3;
 			final_map[index].phys = final_map[index].virt;
-			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+			final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			tlb_addr_save = gd->arch.tlb_addr;
@@ -1323,10 +1323,10 @@
 		ea_size = gd->ram_size;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
-		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+		ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	else
 		printf("Error: No enough space for secure memory.\n");
 #endif
@@ -1433,7 +1433,7 @@
 	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		debug("No need to run again, skip %s\n", __func__);
 
@@ -1442,11 +1442,11 @@
 #endif
 
 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+	if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
+					  CFG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1458,17 +1458,17 @@
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->bd->bi_dram[0].size >
-				CONFIG_SYS_MEM_RESERVE_SECURE) {
+				CFG_SYS_MEM_RESERVE_SECURE) {
 		gd->bd->bi_dram[0].size -=
-				CONFIG_SYS_MEM_RESERVE_SECURE;
+				CFG_SYS_MEM_RESERVE_SECURE;
 		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+		gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	}
-#endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
+#endif	/* CFG_SYS_MEM_RESERVE_SECURE */
 
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
@@ -1520,7 +1520,7 @@
 	}
 #endif
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	debug("%s is called. gd->ram_size is reduced to %lu\n",
 	      __func__, (ulong)gd->ram_size);
 #endif
@@ -1580,7 +1580,7 @@
 	} else {
 		mmu_change_region_attr(
 					CFG_SYS_SDRAM_BASE,
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
@@ -1589,10 +1589,10 @@
 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 #endif
-		if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+		if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
 		    CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1601,7 +1601,7 @@
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK3_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE -
+					CFG_SYS_DDR_BLOCK1_SIZE -
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1611,9 +1611,9 @@
 #endif
 		{
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 9119d60..6f3fe7c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -116,10 +116,10 @@
 Environment Variables
 =====================
 mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
-		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+		the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 mcmemsize:	MC DRAM block size in hex. If this variable is not defined, the value
-		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+		CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 mcinitcmd:	This environment variable is defined to initiate MC and DPL deployment
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 4880a31..e3c3fc6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -10,7 +10,7 @@
 #include <fsl_sec.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index e47d3af..333d7e2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -9,7 +9,7 @@
 #include <asm/arch-fsl-layerscape/fsl_portals.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 89a6262..359cbc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -531,7 +531,7 @@
 
 	porsr1 = in_be32(&gur->porsr1);
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
-	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
 	out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
@@ -643,8 +643,8 @@
 	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
 		 | SCFG_RD_QOS1_PFE2_QOS));
 
-	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
-	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+	ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
 		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
 }
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3a4b665..61fced4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -116,7 +116,7 @@
 #endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifndef CFG_SYS_MEM_RESERVE_SECURE
 #error Need secure RAM for PPA
 #endif
 	/*
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 540436b..c0e8726 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -198,7 +198,7 @@
 		goto out;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * The SEC Firmware must be stored in secure memory.
 	 * Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@
 	sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
 			gd->arch.tlb_size;
 #else
-#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
 #endif
 
 	/* Align SEC Firmware base address to 4K */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0669222..c9c72e3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -20,13 +20,13 @@
  * Reserve secure memory
  * To be aligned with MMU block size
  */
-#define CONFIG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
+#define CFG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
-#define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CFG_SYS_PAGE_SIZE		0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
@@ -37,8 +37,8 @@
 #define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0x06000000
@@ -96,7 +96,7 @@
 
 #elif defined(CONFIG_ARCH_LS1088A)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
-#define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CFG_SYS_PAGE_SIZE		0x10000
 
 #define	SRDS_MAX_LANES	4
 #define	SRDS_BITS_PER_LANE	4
@@ -122,8 +122,8 @@
 #define SMMU_BASE			0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
 #define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
@@ -141,15 +141,15 @@
 #endif
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
 
-#define CONFIG_SYS_PAGE_SIZE			0x10000
+#define CFG_SYS_PAGE_SIZE			0x10000
 
 #define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
 #define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@@ -192,8 +192,8 @@
 #define SMMU_BASE				0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
 
@@ -212,8 +212,8 @@
 #define CFG_SYS_NUM_FMAN			1
 #define CFG_SYS_NUM_FM1_DTSEC		7
 #define CFG_SYS_NUM_FM1_10GEC		1
-#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1
@@ -251,15 +251,15 @@
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CFG_SYS_NUM_FMAN			1
 #define CFG_SYS_NUM_FM1_DTSEC		8
 #define CFG_SYS_NUM_FM1_10GEC		2
-#define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 9cddb41..d5f63f4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -75,7 +75,7 @@
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
 	SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
-		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+		CFG_SYS_XHCI_USB##usb_num##_ADDR)
 
 #define SET_SATA_ICID(compat, streamid) \
 	SET_SCFG_ICID(compat, streamid, sata_icid,\
@@ -142,7 +142,7 @@
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
 	SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
-		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+		CFG_SYS_XHCI_USB##usb_num##_ADDR)
 
 #define SET_SATA_ICID(sata_num, compat, streamid) \
 	SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 64dc7c8..9794db0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -11,11 +11,11 @@
 #include <linux/bitops.h>
 #endif
 
-#define CONFIG_SYS_DCSRBAR			0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CFG_SYS_DCSRBAR			0x20000000
+#define CFG_SYS_DCSR_DCFG_ADDR	(CFG_SYS_DCSRBAR + 0x00140000)
 
 #define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
 #define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CFG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
@@ -30,37 +30,37 @@
 #define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CFG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CFG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CFG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CFG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 #define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
-#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+#define CFG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CFG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
-						CONFIG_SYS_BMAN_MEM_BASE)
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0x508000000
+#define CFG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CFG_SYS_BMAN_MEM_BASE)
+#define CFG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0x500000000
+#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0x3680
 
 #define CFG_SYS_FSL_TIMER_ADDR		0x02b00000
 
@@ -134,20 +134,20 @@
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 #define TP_INIT_PER_CLUSTER     4
 
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		0x01000000
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0x01000000
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	0x01000000
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW	0x01000000
 #endif
 
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cd11240..ca5e333 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -33,7 +33,7 @@
 #define FSL_ESDHC1_BASE_ADDR			CFG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #endif
 #define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
@@ -67,8 +67,8 @@
 #define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
 #define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
 
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
@@ -105,7 +105,7 @@
 #define GPU_BASE_ADDR				(CONFIG_SYS_IMMR + 0x0e0c0000)
 
 /* SFP */
-#define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
 #define CFG_SYS_FSL_SEC_OFFSET		0x07000000ull
@@ -173,7 +173,7 @@
 #endif
 
 /* Security Monitor */
-#define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
 
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 6de431f..3ad78cb 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -23,7 +23,7 @@
 #define CFG_SYS_NS16550_CLK		13000000
 #endif
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
 
 /* NAND */
@@ -49,7 +49,7 @@
 
 /* USB OHCI */
 #if defined(CONFIG_USB_OHCI_LPC32XX)
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		USB_BASE
+#define CFG_SYS_USB_OHCI_REGS_BASE		USB_BASE
 #endif
 
 #endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 62026bda..6413a30 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -11,36 +11,36 @@
 #define OCRAM_BASE_S_ADDR			0x10010000
 #define OCRAM_S_SIZE				0x00010000
 
-#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CFG_SYS_DCSRBAR			0x20000000
 
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
-#define SYS_FSL_DCSR_RCPM_ADDR	(CONFIG_SYS_DCSRBAR + 0x00222000)
+#define CFG_SYS_DCSR_DCFG_ADDR	(CFG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR	(CFG_SYS_DCSRBAR + 0x00222000)
 
 #define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CFG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
 #define CFG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
 #define CFG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
-#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
 #define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CFG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CFG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
 #define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 
 #define CFG_SYS_FSL_SEC_OFFSET		0x00700000
 #define CFG_SYS_FSL_JR0_OFFSET		0x00710000
-#define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
-#define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
+#define CFG_SYS_TSEC1_OFFSET			0x01d10000
+#define CFG_SYS_MDIO1_OFFSET			0x01d24000
 
-#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index b0acf67..a0c3da7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -42,24 +42,24 @@
 
 #define DCFG_DCSR_PORCR1		0
 
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		CONFIG_SYS_IMMR
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0xf
 #else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
 #endif
 
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fb5ded8..acd8c69 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -12,14 +12,14 @@
 	{ .compat = name, \
 	  .id = { idA }, .num_ids = 1, \
 	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA, idB }, .num_ids = 2, \
 	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 /*
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index d5c0ed8..a0ab3a0 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -899,9 +899,9 @@
  * Generic timer support
  */
 #ifdef CONFIG_MX31_CLK32
-#define	CONFIG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
+#define	CFG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
 #else
-#define	CONFIG_SYS_TIMER_RATE	32768
+#define	CFG_SYS_TIMER_RATE	32768
 #endif
 
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
index 5b12d90..eb1ddca 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -36,6 +36,6 @@
 #define GPT_FREE_RUNNING		0xFFFF
 
 /* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ_CLOCK		((27 * 1000 * 1000) / GPT_PRESCALER_128)
+#define CFG_SYS_HZ_CLOCK		((27 * 1000 * 1000) / GPT_PRESCALER_128)
 
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 3525f22..241b449 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -18,6 +18,6 @@
 #endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
-#define CONFIG_SYS_TCLK		24000000
+#define CFG_SYS_TCLK		24000000
 
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index cd6112d..9e746e3 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -54,7 +54,7 @@
 	unsigned long tlb_emerg;
 #endif
 #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 #define MEM_RESERVE_SECURE_SECURED	0x1
 #define MEM_RESERVE_SECURE_MAINTAINED	0x2
 #define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 826e09e..5e6eaad 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -29,7 +29,7 @@
 	struct bd_info *bd = gd->bd;
 
 	bdinfo_print_num_l("arch_number", bd->bi_arch_number);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
 		bdinfo_print_num_ll("Secure ram",
 				    gd->arch.secure_ram &
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index bbaaaa4..d05314e 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -11,7 +11,7 @@
 #include <config.h>
 #include <common.h>
 
-struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 static void pl310_cache_sync(void)
 {
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index a2bf2e5..1a589c7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -152,7 +152,7 @@
 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
 	      gd->arch.tlb_addr + gd->arch.tlb_size);
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
 	 * with location within secure ram.
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index a54c84b..7cf7d16 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -83,8 +83,8 @@
  */
 
 _start:
-#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
-	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
+#ifdef CFG_SYS_DV_NOR_BOOT_CFG
+	.word	CFG_SYS_DV_NOR_BOOT_CFG
 #endif
 	ARM_VECTORS
 #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c
index c744027..09ac66d 100644
--- a/arch/arm/mach-at91/arm920t/clock.c
+++ b/arch/arm/mach-at91/arm920t/clock.c
@@ -26,7 +26,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -107,7 +107,7 @@
 {
 	unsigned freq, mckr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -120,7 +120,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;
diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c
index 44c079c..9bf03fd 100644
--- a/arch/arm/mach-at91/arm920t/cpu.c
+++ b/arch/arm/mach-at91/arm920t/cpu.c
@@ -16,11 +16,11 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
 {
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 }
diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index 3b91a0c..6b7d3cb 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
@@ -94,11 +94,11 @@
 	.word AT91_ASM_MC_SMC_CSR0
 	.word CONFIG_SYS_SMC_CSR0_VAL
 	.word AT91_ASM_PMC_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
+	.word CFG_SYS_PLLAR_VAL
 	.word AT91_ASM_PMC_PLLBR
 	.word CONFIG_SYS_PLLBR_VAL
 	.word AT91_ASM_PMC_MCKR
-	.word CONFIG_SYS_MCKR_VAL
+	.word CFG_SYS_MCKR_VAL
 SMRDATAE:
 	/* here there's a delay */
 SMRDATA1:
@@ -107,17 +107,17 @@
 	.word AT91_ASM_PIOC_BSR
 	.word CONFIG_SYS_PIOC_BSR_VAL
 	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word CFG_SYS_PIOC_PDR_VAL
 	.word AT91_ASM_MC_EBI_CSA
 	.word CONFIG_SYS_EBI_CSA_VAL
 	.word AT91_ASM_MC_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
+	.word CFG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
+	.word CFG_SYS_SDRC_MR_VAL
 	.word CFG_SYS_SDRAM
 	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CFG_SYS_SDRC_MR_VAL1
 	.word CFG_SYS_SDRAM
 	.word CFG_SYS_SDRAM_VAL
 	.word CFG_SYS_SDRAM
@@ -135,15 +135,15 @@
 	.word CFG_SYS_SDRAM
 	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CFG_SYS_SDRC_MR_VAL2
 	.word CFG_SYS_SDRAM1
 	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
+	.word CFG_SYS_SDRC_TR_VAL
 	.word CFG_SYS_SDRAM
 	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CFG_SYS_SDRC_MR_VAL3
 	.word CFG_SYS_SDRAM
 	.word CFG_SYS_SDRAM_VAL
 SMRDATA1E:
diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c
index c400e87..8ef5764 100644
--- a/arch/arm/mach-at91/arm920t/timer.c
+++ b/arch/arm/mach-at91/arm920t/timer.c
@@ -27,7 +27,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
 
 int timer_init(void)
 {
@@ -92,7 +92,7 @@
 	u32 endtime;
 	signed long diff;
 
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo = CFG_SYS_HZ_CLOCK / 1000;
 	tmo *= usec;
 	tmo /= 1000;
 
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c68e0c0..013daf4 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -26,7 +26,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -115,7 +115,7 @@
 {
 	unsigned freq, mckr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -128,7 +128,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;
diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c
index 761edb6..5e84b0a 100644
--- a/arch/arm/mach-at91/arm926ejs/cpu.c
+++ b/arch/arm/mach-at91/arm926ejs/cpu.c
@@ -15,13 +15,13 @@
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
 {
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 }
 
 void arch_preboot_os(void)
diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index ecfe589..e159a74 100644
--- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
@@ -21,8 +21,8 @@
 #ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/at91sam9_matrix.h>
 #endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#ifndef CFG_SYS_MATRIX_EBICSA_VAL
+#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL
 #endif
 
 .globl lowlevel_init
@@ -67,7 +67,7 @@
 	ldr	r1, =(AT91_ASM_PMC_MOR)
 	ldr	r2, =(AT91_ASM_PMC_SR)
 	/* Main oscillator Enable register PMC_MOR: */
-	ldr	r0, =CONFIG_SYS_MOR_VAL
+	ldr	r0, =CFG_SYS_MOR_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
@@ -85,7 +85,7 @@
  * ----------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_PLLAR)
-	ldr	r0, =CONFIG_SYS_PLLAR_VAL
+	ldr	r0, =CFG_SYS_PLLAR_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status register to detect when the PLLA is locked */
@@ -105,7 +105,7 @@
 	ldr	r1, =(AT91_ASM_PMC_MCKR)
 
 	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =CONFIG_SYS_MCKR1_VAL
+	ldr	r0, =CFG_SYS_MCKR1_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Master clock is ready */
@@ -116,7 +116,7 @@
 	cmp	r3, #AT91_PMC_IXR_MCKRDY
 	bne	MCKRDY_Loop
 
-	ldr	r0, =CONFIG_SYS_MCKR2_VAL
+	ldr	r0, =CFG_SYS_MCKR2_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Master clock is ready */
@@ -158,53 +158,53 @@
 
 SMRDATA:
 	.word AT91_ASM_WDT_MR
-	.word CONFIG_SYS_WDTC_WDMR_VAL
+	.word CFG_SYS_WDTC_WDMR_VAL
 	/* configure PIOx as EBI0 D[16-31] */
 #if defined(CONFIG_AT91SAM9263)
 	.word AT91_ASM_PIOD_PDR
-	.word CONFIG_SYS_PIOD_PDR_VAL1
+	.word CFG_SYS_PIOD_PDR_VAL1
 	.word AT91_ASM_PIOD_PUDR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word CFG_SYS_PIOD_PPUDR_VAL
 	.word AT91_ASM_PIOD_ASR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word CFG_SYS_PIOD_PPUDR_VAL
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
 	|| defined(CONFIG_AT91SAM9G20)
 	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL1
+	.word CFG_SYS_PIOC_PDR_VAL1
 	.word AT91_ASM_PIOC_PUDR
-	.word CONFIG_SYS_PIOC_PPUDR_VAL
+	.word CFG_SYS_PIOC_PPUDR_VAL
 #endif
 	.word AT91_ASM_MATRIX_CSA0
-	.word CONFIG_SYS_MATRIX_EBICSA_VAL
+	.word CFG_SYS_MATRIX_EBICSA_VAL
 
 	/* flash */
 	.word AT91_ASM_SMC_MODE0
-	.word CONFIG_SYS_SMC0_MODE0_VAL
+	.word CFG_SYS_SMC0_MODE0_VAL
 
 	.word AT91_ASM_SMC_CYCLE0
-	.word CONFIG_SYS_SMC0_CYCLE0_VAL
+	.word CFG_SYS_SMC0_CYCLE0_VAL
 
 	.word AT91_ASM_SMC_PULSE0
-	.word CONFIG_SYS_SMC0_PULSE0_VAL
+	.word CFG_SYS_SMC0_PULSE0_VAL
 
 	.word AT91_ASM_SMC_SETUP0
-	.word CONFIG_SYS_SMC0_SETUP0_VAL
+	.word CFG_SYS_SMC0_SETUP0_VAL
 
 SMRDATA1:
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CFG_SYS_SDRC_MR_VAL1
 	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL1
+	.word CFG_SYS_SDRC_TR_VAL1
 	.word AT91_ASM_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
+	.word CFG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_SDRAMC_MDR
-	.word CONFIG_SYS_SDRC_MDR_VAL
+	.word CFG_SYS_SDRC_MDR_VAL
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CFG_SYS_SDRC_MR_VAL2
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL1
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CFG_SYS_SDRC_MR_VAL3
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL2
 	.word CFG_SYS_SDRAM_BASE
@@ -222,20 +222,20 @@
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL9
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL4
+	.word CFG_SYS_SDRC_MR_VAL4
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL10
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL5
+	.word CFG_SYS_SDRC_MR_VAL5
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL11
 	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL2
+	.word CFG_SYS_SDRC_TR_VAL2
 	.word CFG_SYS_SDRAM_BASE
 	.word CFG_SYS_SDRAM_VAL12
 	/* User reset enable*/
 	.word AT91_ASM_RSTC_MR
-	.word CONFIG_SYS_RSTC_RMR_VAL
+	.word CFG_SYS_RSTC_RMR_VAL
 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 	/* MATRIX_MCFG - REMAP all masters */
 	.word AT91_ASM_MATRIX_MCFG
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index aa6bb6b..6bfa02d 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -28,7 +28,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -58,7 +58,7 @@
 {
 	unsigned freq, mckr;
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -71,7 +71,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;
@@ -271,7 +271,7 @@
 	clk_source = regval & AT91_PMC_PCR_GCKCSS;
 	switch (clk_source) {
 	case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
-		freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+		freq = CFG_SYS_AT91_SLOW_CLOCK;
 		break;
 	case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
 		freq = gd->arch.main_clk_rate_hz;
diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 9b37534..616621a 100644
--- a/arch/arm/mach-at91/armv7/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c
@@ -18,8 +18,8 @@
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
@@ -27,7 +27,7 @@
 #if defined(CONFIG_CLK_CCF)
 	return 0;
 #else
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 #endif
 }
 
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 2daeb4f..103db26 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -128,7 +128,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index d5de8d5..2b252f1 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -112,7 +112,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index c9fff934..0aa1862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -127,7 +127,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 5880325..22116f3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -132,7 +132,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 8f9155c..b2c074e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -112,7 +112,7 @@
 #define ATMEL_BASE_CS5		0x60000000	/* Compact Flash Slot 1 */
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index e3c494c..0efb4a9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -162,7 +162,7 @@
 #endif
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe3c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index c08d19c..47c7c72 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h
@@ -140,7 +140,7 @@
 #define ATMEL_CPU_NAME	get_cpu_name()
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe4c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe4c
 
 /*
  * Other misc defines
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index 5ff20e9..567cdd3 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -238,7 +238,7 @@
 #define cpu_is_sama5d2	_cpu_is_sama5d2
 
 /* PIT Timer(PIT_PIIR) */
-#define CONFIG_SYS_TIMER_COUNTER	0xf804803c
+#define CFG_SYS_TIMER_COUNTER	0xf804803c
 
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 83f18a8..9efcf5f 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -185,7 +185,7 @@
 #define CPU_HAS_PCR
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe3c
 
 /*
  * PMECC table in ROM
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index e2edb6a..9c80286 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -217,7 +217,7 @@
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfc06863c
+#define CFG_SYS_TIMER_COUNTER	0xfc06863c
 
 /*
  * No PMECC Galois table in ROM
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index ea19ec3..dfba9f7 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -101,17 +101,17 @@
 	at91_pllicpr_init(0x00);
 
 	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
-	at91_plla_init(CONFIG_SYS_AT91_PLLA);
+	at91_plla_init(CFG_SYS_AT91_PLLA);
 
 	/* PCK = PLLA = 2 * MCK */
-	at91_mck_init(CONFIG_SYS_MCKR);
+	at91_mck_init(CFG_SYS_MCKR);
 
 	/* Switch MCK on PLLA output */
-	at91_mck_init(CONFIG_SYS_MCKR_CSS);
+	at91_mck_init(CFG_SYS_MCKR_CSS);
 
-#if defined(CONFIG_SYS_AT91_PLLB)
+#if defined(CFG_SYS_AT91_PLLB)
 	/* Configure PLLB */
-	at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+	at91_pllb_init(CFG_SYS_AT91_PLLB);
 #endif
 
 	/* Enable External Reset */
@@ -120,7 +120,7 @@
 	/* Initialize matrix */
 	matrix_init();
 
-	gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
+	gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK;
 	/*
 	 * init timer long enough for using in spl.
 	 */
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 217ed12..a30c4f6 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -124,7 +124,7 @@
 	/* PMC configuration */
 	at91_pmc_init();
 
-	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 
 	matrix_init();
 
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index 0f68f9f..dae6026 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -42,7 +42,7 @@
 	int pll_out;
 	unsigned int pll_base;
 
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
+	pll_out = CFG_SYS_OSCIN_FREQ;
 
 	if (id == DAVINCI_AUXCLK_CLKID)
 		goto out;
diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c
index 2319ac6..08c8f59 100644
--- a/arch/arm/mach-davinci/da850_lowlevel.c
+++ b/arch/arm/mach-davinci/da850_lowlevel.c
@@ -185,9 +185,9 @@
 		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 	}
 	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
-	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+	writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 
-	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+	if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
 		/* DDR2 */
 		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 			(1 << DDR_SLEW_DDR_PDENA_BIT) |
@@ -211,19 +211,19 @@
 	 * At the same time, set the TIMUNLOCK bit to allow changing
 	 * the timing registers
 	 */
-	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+	tmp = CFG_SYS_DA850_DDR2_SDBCR;
 	tmp &= ~DV_DDR_BOOTUNLOCK;
 	tmp |= DV_DDR_TIMUNLOCK;
 	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
 	/* write memory configuration and timing */
-	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+	if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
 		/* MOBILE DDR only*/
-		writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+		writel(CFG_SYS_DA850_DDR2_SDBCR2,
 			&dv_ddr2_regs_ctrl->sdbcr2);
 	}
-	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+	writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
 	/* clear the TIMUNLOCK bit and write the value of the CL field */
 	tmp &= ~DV_DDR_TIMUNLOCK;
@@ -233,7 +233,7 @@
 	 * LPMODEN and MCLKSTOPEN must be set!
 	 * Without this bits set, PSC don;t switch states !!
 	 */
-	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+	writel(CFG_SYS_DA850_DDR2_SDRCR |
 		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
 		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
 		&dv_ddr2_regs_ctrl->sdrcr);
@@ -246,7 +246,7 @@
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
 		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
-	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+	writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 
 	return 0;
 }
@@ -265,7 +265,7 @@
 	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
 
 	dv_maskbits(&davinci_syscfg_regs->suspsrc,
-		CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+		CFG_SYS_DA850_SYSCFG_SUSPSRC);
 
 	/* configure pinmux settings */
 	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
@@ -273,8 +273,8 @@
 
 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 	/* PLL setup */
-	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
-	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+	da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM);
+	da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM);
 #endif
 	/* setup CSn config */
 #if defined(CONFIG_SYS_DA850_CS2CFG)
diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c
index 43e0574..83c190b 100644
--- a/arch/arm/mach-davinci/timer.c
+++ b/arch/arm/mach-davinci/timer.c
@@ -32,7 +32,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct davinci_timer * const timer =
-	(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+	(struct davinci_timer *)CFG_SYS_TIMERBASE;
 
 #define TIMER_LOAD_VAL	0xffffffff
 
@@ -47,7 +47,7 @@
 	writel(0x0, &timer->tim34);
 	writel(TIMER_LOAD_VAL, &timer->prd34);
 	writel(2 << 22, &timer->tcr);
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
 	gd->arch.timer_reset_value = 0;
 
 	return(0);
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index f518539..553dac7 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -141,7 +141,7 @@
 {
 	int upto, todo;
 	int i, timeout = 100;
-	struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
+	struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
 
 	set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
 	/* set the spi1 GPIO */
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 0e76786..06ee608 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -248,13 +248,13 @@
 	int end;
 
 	/* Calculate the image set end,
-	 * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
-	 * we use CONFIG_SYS_UBOOT_BASE
+	 * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
+	 * we use CFG_SYS_UBOOT_BASE
 	 * Otherwise, use the calculated address
 	 */
 	end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
-	if (end <= CONFIG_SYS_UBOOT_BASE)
-		end = CONFIG_SYS_UBOOT_BASE;
+	if (end <= CFG_SYS_UBOOT_BASE)
+		end = CFG_SYS_UBOOT_BASE;
 	else
 		end = ROUND(end, SZ_1K);
 
diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S
index b42cc3e..6ec38dc 100644
--- a/arch/arm/mach-imx/mx5/lowlevel_init.S
+++ b/arch/arm/mach-imx/mx5/lowlevel_init.S
@@ -205,7 +205,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
@@ -215,7 +215,7 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 
 	setup_pll PLL3_BASE_ADDR, 216
@@ -240,10 +240,10 @@
 
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+	ldr r1, =CFG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	/* Restore the default values in the Gate registers */
@@ -378,7 +378,7 @@
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
+#if defined(CFG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23
diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk
index 9cc1f9e..7bc8af8 100644
--- a/arch/arm/mach-k3/config_secure.mk
+++ b/arch/arm/mach-k3/config_secure.mk
@@ -30,7 +30,7 @@
 	$(call if_changed,mkfitimage)
 
 MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
 
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 4734e4c..dc97bac 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -23,7 +23,7 @@
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	freq = CONFIG_SYS_HZ_CLOCK;
+	freq = CFG_SYS_HZ_CLOCK;
 
 	addr = hextoul(argv[1], NULL);
 
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 98a8f05..424c32a 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -263,7 +263,7 @@
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
 #define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
-#define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
+#define KS2_MSMC_DST_SEG_BASE		(CFG_SYS_LPAE_SDRAM_BASE >> \
 					KS2_MSMC_SEG_SIZE_SHIFT)
 
 /* Device speed */
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 5186f6e..a2781e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -52,8 +52,8 @@
 
 /* Use common timer */
 #ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
-#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_TCLK
+#define CFG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
+#define CFG_SYS_TIMER_RATE		CFG_SYS_TCLK
 #endif
 
 #endif /* _KW_CONFIG_H */
diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
index c44eacf..d3a3a83 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
@@ -15,6 +15,6 @@
 #define KW_REGS_PHY_BASE		KW88F6192_REGS_PHYS_BASE
 
 /* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK	  166000000 /* 166MHz */
+#define CFG_SYS_TCLK	  166000000 /* 166MHz */
 
 #endif /* _CONFIG_KW88F6192_H */
diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index f86cd0b..7f8e156 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
@@ -15,7 +15,7 @@
 #define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE
 
 /* TCLK Core Clock definition */
-#define CONFIG_SYS_TCLK			((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK			((readl(CONFIG_SAR_REG) & BIT(21)) ? \
 					166666667 : 200000000)
 
 #endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1f8cdf8..67ad5e5 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -659,7 +659,7 @@
 void v7_outer_cache_enable(void)
 {
 	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+		(struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	/* The L2 cache is already disabled at this point */
 
@@ -691,7 +691,7 @@
 void v7_outer_cache_disable(void)
 {
 	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+		(struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 3b96188..e6383d4 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -54,7 +54,7 @@
 
 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
-#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
+#define CFG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
 #define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
@@ -146,7 +146,7 @@
 #define BOOT_FROM_UART		0x30
 #define BOOT_FROM_SPI		0x38
 
-#define CONFIG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(20)) ? \
 				 200000000 : 166000000)
 #elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
@@ -169,7 +169,7 @@
 #define BOOT_FROM_MMC		0x30
 #define BOOT_FROM_MMC_ALT	0x31
 
-#define CONFIG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(15)) ? \
 				 200000000 : 250000000)
 #elif defined(CONFIG_ARMADA_MSYS)
 /* SAR values for MSYS */
@@ -188,7 +188,7 @@
 #define BOOT_FROM_UART		0x2
 #define BOOT_FROM_SPI		0x3
 
-#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+#define CFG_SYS_TCLK		200000000	/* 200MHz */
 #elif defined(CONFIG_ARMADA_XP)
 /* SAR values for Armada XP */
 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
@@ -209,7 +209,7 @@
 #define BOOT_FROM_UART		0x2
 #define BOOT_FROM_SPI		0x3
 
-#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+#define CFG_SYS_TCLK		250000000	/* 250MHz */
 #endif
 
 #endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S
index 60c2072..6c9783a 100644
--- a/arch/arm/mach-mvebu/lowlevel.S
+++ b/arch/arm/mach-mvebu/lowlevel.S
@@ -35,10 +35,10 @@
 	 * Disable L2 cache
 	 *
 	 * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
-	 *       but CONFIG_SYS_PL310_BASE is already calculated from base
+	 *       but CFG_SYS_PL310_BASE is already calculated from base
 	 *       address SOC_REGS_PHY_BASE.
 	 */
-	ldr	r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+	ldr	r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
 	ldr	r0, [r1, #L2X0_CTRL_OFF]
 	bic	r0, #L2X0_CTRL_EN
 	str	r0, [r1, #L2X0_CTRL_OFF]
diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
index cba2e34..ed4b1ca 100644
--- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
+++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
@@ -11,7 +11,7 @@
 
 void set_pl310_ctrl(u32 enable)
 {
-	struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	writel(enable, &pl310->pl310_ctrl);
 }
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index f76262b..24ddcdb 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -102,7 +102,7 @@
 ifdef CONFIG_SPL_LOAD_FIT
 
 MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
 
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 803dc7f..1919748 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c
@@ -124,11 +124,11 @@
 #if defined(CONFIG_NOR)
 	case MTD_DEV_TYPE_NOR:
 		gpmc_regs = gpmc_regs_nor;
-		base = CONFIG_SYS_FLASH_BASE;
-		size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+		base = CFG_SYS_FLASH_BASE;
+		size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+		      ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+		      ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+		      ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
 		                                              GPMC_SIZE_16M)));
 		break;
 #endif
@@ -142,7 +142,7 @@
 #if defined(CONFIG_CMD_ONENAND)
 	case MTD_DEV_TYPE_ONENAND:
 		gpmc_regs = gpmc_regs_onenand;
-		base = CONFIG_SYS_ONENAND_BASE;
+		base = CFG_SYS_ONENAND_BASE;
 		size = GPMC_SIZE_128M;
 		break;
 #endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 00d91c1..71fdf5b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE;
 static ulong get_timer_masked(void);
 
 /*
diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
index 0e9fe0d..ee0aa94 100644
--- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h
+++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
@@ -18,6 +18,6 @@
 #define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
 
 /* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+#define CFG_SYS_TCLK			166000000 /* 166MHz */
 
 #endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c
index d7ea2e3..b373e59 100644
--- a/arch/arm/mach-orion5x/timer.c
+++ b/arch/arm/mach-orion5x/timer.c
@@ -74,7 +74,7 @@
 static inline ulong read_timer(void)
 {
 	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
-	      / (CONFIG_SYS_TCLK / 1000);
+	      / (CFG_SYS_TCLK / 1000);
 }
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -92,7 +92,7 @@
 	} else {
 		/* we have an overflow ... */
 		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+			(TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now;
 	}
 	lastdec = now;
 
@@ -115,7 +115,7 @@
 	ulong delayticks;
 
 	current = uboot_cntr_val();
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+	delayticks = (usec * (CFG_SYS_TCLK / 1000000));
 
 	if (current < delayticks) {
 		delayticks -= current;
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h
index 28669e3..485ea7e 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h
@@ -24,7 +24,7 @@
 #define MSTP11_BITS	0x00000000
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
 
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h
index 37d134c..2006ad58 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h
@@ -14,7 +14,7 @@
  */
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h
index 06db64a..cc1b00d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7792.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h
@@ -24,6 +24,6 @@
 #define MSTP11_BITS	0x00000008
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
 
 #endif /* __ASM_ARCH_R8A7792_H */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h
index 85f59d9..02f4286 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7793.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h
@@ -15,7 +15,7 @@
  */
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h
index 2bd6e46..a2a949d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7794.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h
@@ -24,7 +24,7 @@
 #define MSTP11_BITS	0x000001C0
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define R8A7794_CUT_ES2		2
 #define IS_R8A7794_ES2()	\
diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c
index ba06535..293c23b 100644
--- a/arch/arm/mach-rmobile/timer.c
+++ b/arch/arm/mach-rmobile/timer.c
@@ -40,8 +40,8 @@
 {
 	u64 timer = get_cpu_global_timer();
 
-	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
-	do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
+	timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
+	do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
 	return timer;
 }
 
@@ -65,7 +65,7 @@
 	u64 wait;
 
 	start = get_cpu_global_timer();
-	wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+	wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
 	do {
 		current = get_cpu_global_timer();
 	} while ((current - start) < wait);
@@ -83,5 +83,5 @@
 
 ulong get_tbclk(void)
 {
-	return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+	return (ulong)(CFG_SYS_CPU_CLK >> 2);
 }
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 9c19157..5b5a81a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -34,7 +34,7 @@
 
 #ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 #endif
 
 struct bsel bsel_str[] = {
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 7ce888d..93c9e8b 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -60,7 +60,7 @@
 
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
 	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
 
@@ -256,7 +256,7 @@
 	/* If we're still in OCRAM, don't set the XN bit on it */
 	if (!(gd->flags & GD_FLG_RELOC)) {
 		set_section_dcache(
-			CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+			CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
 			DCACHE_WRITETHROUGH);
 	}
 
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 4edf4f9..e7500c1 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -31,7 +31,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 2c567ed..9edbbf4 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -41,7 +41,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BOOTROM_SHARED_MEM_SIZE		0x800	/* 2KB */
-#define BOOTROM_SHARED_MEM_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+#define BOOTROM_SHARED_MEM_ADDR		(CFG_SYS_INIT_RAM_ADDR + \
 					 SOCFPGA_PHYS_OCRAM_SIZE - \
 					 BOOTROM_SHARED_MEM_SIZE)
 #define RST_STATUS_SHARED_ADDR		(BOOTROM_SHARED_MEM_ADDR + 0x438)
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index a58f1cf..d9e8c84 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -10,7 +10,7 @@
 
 #define TIMER_LOAD_VAL		0xFFFFFFFF
 
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
 
 /*
  * Timer initialization
diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c
index f9fd4fe..05a9134 100644
--- a/arch/arm/mach-u8500/cache.c
+++ b/arch/arm/mach-u8500/cache.c
@@ -22,7 +22,7 @@
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_disable(void)
 {
-	struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	/*
 	 * Linux expects the L2 cache to be turned off by the bootloader.
diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c
index a40bdf1..58247c2 100644
--- a/arch/arm/mach-uniphier/arm32/timer.c
+++ b/arch/arm/mach-uniphier/arm32/timer.c
@@ -10,7 +10,7 @@
 #include "arm-mpcore.h"
 
 #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
 
 static void *get_global_timer_base(void)
 {
diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c
index 739cb29..b471412 100644
--- a/arch/arm/mach-versatile/timer.c
+++ b/arch/arm/mach-versatile/timer.c
@@ -36,9 +36,9 @@
 	ulong	tmr_ctrl_val;
 
 	/* 1st disable the Timer */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
 	tmr_ctrl_val &= ~TIMER_ENABLE;
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
 
 	/*
 	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -52,11 +52,11 @@
 	 * Tmr Siz : 16 Bit Counter
 	 * Tmr in Wrapping Mode
 	 */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
 	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
 	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
 
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
 
 	return 0;
 }
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index e44656d..6d87908 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -92,7 +92,7 @@
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
-	wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
 	wdog_module |= (wdog_module / 8192);
 	out_be16(&wdp->mr, wdog_module);
 
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 87effa7..10be738 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -47,36 +47,36 @@
 	out_be16(&wdog->cr, 0);
 #endif
 
-	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+	out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
 
 	/* Port configuration */
 	out_8(&gpio->par_cs, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+	out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
-	out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
-	out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+	out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
-	out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+	out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -108,8 +108,8 @@
 #endif
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #endif
 
 	icache_enable();
diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c
index f41f977..6b08a12 100644
--- a/arch/m68k/cpu/mcf523x/speed.c
+++ b/arch/m68k/cpu/mcf523x/speed.c
@@ -29,7 +29,7 @@
 	while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
 		;
 
-	gd->bus_clk = CONFIG_SYS_CLK;
+	gd->bus_clk = CFG_SYS_CLK;
 	gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 4c9c96d..d2a21c3 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -91,10 +91,10 @@
 	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
@@ -116,7 +116,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l  #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 8f72ef5..d21d82f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -132,11 +132,11 @@
 
 	if (cpu_model)
 		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
-		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+		       cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
 	else
 		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
 		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
-		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+		       pin, prn, strmhz(buf, CFG_SYS_CLK));
 
 	return 0;
 }
@@ -284,7 +284,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
-			strmhz(buf, CONFIG_SYS_CLK));
+			strmhz(buf, CFG_SYS_CLK));
 	return 0;
 };
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -370,7 +370,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
+	       strmhz(buf, CFG_SYS_CLK));
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -394,7 +394,7 @@
 
 	unsigned char resetsource = mbar_readLong(SIM_RSR);
 	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
+	       strmhz(buf, CFG_SYS_CLK));
 
 	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 		printf("Reset:%s%s\n",
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 9d4a10f..99eb61f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -36,31 +36,31 @@
 {
 	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
@@ -214,9 +214,9 @@
 	init_fbcs();
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG =
-	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG =
+	    CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 	CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@@ -335,21 +335,21 @@
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
 	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 
-	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
-	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+	out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
 
 	/* Setup Ports: */
-	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
-	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
-	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
-	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
-	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
-	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
-	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+	out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
 
 	/* Memory Controller: */
 	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@@ -472,8 +472,8 @@
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #endif
 
 	/* enable instruction cache now */
@@ -560,8 +560,8 @@
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 	/* Set speed /PLL */
 	MCFCLOCK_SYNCR =
-	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
-	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+	    MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+	    MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
 	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 
 	MCFGPIO_PBCDPAR = 0xc0;
@@ -573,17 +573,17 @@
 #ifdef	CONFIG_SYS_PFPAR
 	MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 #endif
-#ifdef CONFIG_SYS_PJPAR
-	MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+	MCFGPIO_PJPAR = CFG_SYS_PJPAR;
 #endif
 #ifdef CONFIG_SYS_PSDPAR
 	MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 #endif
-#ifdef CONFIG_SYS_PASPAR
-	MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+	MCFGPIO_PASPAR = CFG_SYS_PASPAR;
 #endif
-#ifdef CONFIG_SYS_PEHLPAR
-	MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+	MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
 #endif
 #ifdef CONFIG_SYS_PQSPAR
 	MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@@ -600,15 +600,15 @@
 #ifdef CONFIG_SYS_PTDPAR
 	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 #endif
-#ifdef CONFIG_SYS_PUAPAR
-	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+	MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
 #endif
 
 #if defined(CONFIG_SYS_DDRD)
 	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 #endif
-#ifdef CONFIG_SYS_DDRUA
-	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+	MCFGPIO_DDRUA = CFG_SYS_DDRUA;
 #endif
 
 	/* FlexBus Chipselect */
@@ -652,10 +652,10 @@
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+		MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
 	} else {
 		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+		MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
 	}
 	return 0;
 }
@@ -678,12 +678,12 @@
 	 *        which is their primary function.
 	 *        ~Jeremy
 	 */
-	mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
-	mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
-	mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
-	mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
 
 	/*
 	 *  dBug Compliance:
diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 045908a..6c76282 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c
@@ -23,19 +23,19 @@
 #if defined(CONFIG_M5208)
 	pll_t *pll = (pll_t *) MMAP_PLL;
 
-	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
-	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+	out_8(&pll->odr, CFG_SYS_PLL_ODR);
+	out_8(&pll->fdr, CFG_SYS_PLL_FDR);
 #endif
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
 
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
 
 #ifdef CONFIG_M5249
 	/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
 	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
 #else
 	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
@@ -43,7 +43,7 @@
 #endif				/* CONFIG_M5249 */
 
 #ifdef CONFIG_M5253
-	pllcr = CONFIG_SYS_PLLCR;
+	pllcr = CFG_SYS_PLLCR;
 #endif				/* CONFIG_M5253 */
 
 	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -52,7 +52,7 @@
 	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
 	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
 	udelay(0x20);		/* Wait for a lock ... */
-#endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif				/* #ifndef CFG_SYS_PLL_BYPASS */
 
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
@@ -68,7 +68,7 @@
 		;
 #endif
 
-	gd->cpu_clk = CONFIG_SYS_CLK;
+	gd->cpu_clk = CFG_SYS_CLK;
 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 6dddbe7..d48d019 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -35,7 +35,7 @@
  */
 _vectors:
 .long	0x00000000		/* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	_start - CONFIG_TEXT_BASE
 #else
 .long	_START
@@ -81,9 +81,9 @@
 
 .text
 
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
     (defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	0x55AA55AA,0xAA55AA55		/* CFM Backdoorkey */
 .long	0xFFFFFFFF			/* all sectors protected */
 .long	0x00000000			/* supervisor/User restriction */
@@ -100,53 +100,53 @@
 
 #if defined(CONFIG_M5208)
 	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.c	%d0, %MBAR
 
 	/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
 	/* Get MBAR2 address */
-	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0
+	move.l	#(CFG_SYS_MBAR2 + 1), %d0
 	 /* Set MBAR2 */
 	movec	%d0, #0xc0e
 #endif
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 1), %d0
 	movec	%d0, %RAMBAR0
 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 
 	/* Initialize RAMBAR1: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
 
 #if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 	/*
 	 * Setup code in SRAM to initialize FLASHBAR,
 	 * if start from internal Flash
 	 */
-	move.l	#(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
-	move.l	#(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR), %a2
+	move.l	#(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+	move.l	#(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+	move.l	#(CFG_SYS_INIT_RAM_ADDR), %a2
 _copy_flash:
 	move.l	(%a0)+, (%a2)+
 	cmp.l	%a0, %a1
 	bgt.s	_copy_flash
-	jmp	CONFIG_SYS_INIT_RAM_ADDR
+	jmp	CFG_SYS_INIT_RAM_ADDR
 
 _flashbar_setup:
 	/* Initialize FLASHBAR: locate internal Flash and validate it */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	move.l	#(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
 	movec	%d0, %FLASHBAR
 	jmp	_after_flashbar_copy.L	/* Force jump to absolute address */
 _flashbar_setup_end:
@@ -154,9 +154,9 @@
 _after_flashbar_copy:
 #else
 	/* Setup code to initialize FLASHBAR, if start from external Memory */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	move.l	#(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
 	movec	%d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
 
 #endif
 #endif
@@ -165,22 +165,22 @@
 	 * therefore no VBR to set
 	 */
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-	move.l	#CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+	move.l	#CFG_SYS_INT_FLASH_BASE, %d0
 #else
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 #endif
 	movec	%d0, %VBR
 #endif
 
 #ifdef CONFIG_M5275
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 /*	movec	%d0, %MBAR */
 
 	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
@@ -195,7 +195,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
index 0659bf6..53a25d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu.c
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -33,7 +33,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5307 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CPU_CLK));
+	       strmhz(buf, CFG_SYS_CPU_CLK));
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 8352940..dad47d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -40,35 +40,35 @@
 {
 	csm_t *csm = (csm_t *)(MMAP_CSM);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
-	defined(CONFIG_SYS_CS0_CTRL))
-	out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
-	out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
+	defined(CFG_SYS_CS0_CTRL))
+	out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
+	out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
-	defined(CONFIG_SYS_CS1_CTRL))
-	out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
-	out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
+	defined(CFG_SYS_CS1_CTRL))
+	out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
+	out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
 #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
-	defined(CONFIG_SYS_CS2_CTRL))
-	out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
-	out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
+	defined(CFG_SYS_CS2_CTRL))
+	out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
+	out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
 #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
-	defined(CONFIG_SYS_CS3_CTRL))
-	out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
-	out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
+	defined(CFG_SYS_CS3_CTRL))
+	out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
+	out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
 	defined(CONFIG_SYS_CS4_CTRL))
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
index 03d9abe..c8d0790 100644
--- a/arch/m68k/cpu/mcf530x/speed.c
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -16,8 +16,8 @@
 int get_clocks(void)
 {
 #if defined(CONFIG_M5307)
-	gd->bus_clk = CONFIG_SYS_CLK;
-	gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+	gd->bus_clk = CFG_SYS_CLK;
+	gd->cpu_clk = CFG_SYS_CPU_CLK;
 #endif
 
 	return 0;
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 644c372..dbe2b54 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -39,7 +39,7 @@
 /* Flash offset is 0 until we setup CS0 */
 .long	0x00000000
 #if defined(CONFIG_M5307) && \
-	   (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+	   (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	_start - CONFIG_TEXT_BASE
 #else
 .long	_START
@@ -92,10 +92,10 @@
 	move.w	#0x2700,%sr
 
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.c	%d0, %MBAR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 1), %d0
 	move.c	%d0, %RAMBAR
 
 	/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
@@ -110,7 +110,7 @@
 	 * therefore no VBR to set
 	 */
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 #endif
 
@@ -125,7 +125,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 1dadffd..8a48d73 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -131,7 +131,7 @@
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
-	wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
 #ifdef CONFIG_M5329
 	out_be16(&wdp->mr, wdog_module / 8192);
 #else
diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 1311f39..844d2cd 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c
@@ -37,34 +37,34 @@
 	out_be32(&scm1->pacrf, 0);
 	out_be32(&scm1->pacrg, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -102,8 +102,8 @@
 	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
 	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
 
-	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
-	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+	out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT);
+	out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
 
 #endif
 #ifdef CONFIG_MCFFEC
@@ -236,36 +236,36 @@
 	/* Port configuration */
 	out_8(&gpio->par_cs, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
 	/* Latch chipselect */
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -327,7 +327,7 @@
 		clrbits_8(&gpio->par_feci2c, 0x00ff);
 		setbits_8(&gpio->par_feci2c,
 			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
-#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+#elif defined(CFG_SYS_UART2_ALT3_GPIO)
 		clrbits_be16(&gpio->par_ssi, 0x0f00);
 		setbits_be16(&gpio->par_ssi,
 			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index dac2229..32ffac08 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c
@@ -252,7 +252,7 @@
 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks(void)
 {
-	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+	gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000;
 	gd->cpu_clk = (gd->bus_clk * 3);
 
 #ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 2672891..72a2f99 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -98,11 +98,11 @@
 
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 #endif
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
@@ -131,7 +131,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l  #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9b3f9f0..1ce2448 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -29,30 +29,30 @@
 	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
 #if !defined(CONFIG_SERIAL_BOOT)
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -208,14 +208,14 @@
 	/* FlexBus Chipselect */
 	init_fbcs();
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/*
 	 * now the flash base address is no longer at 0 (Newer ColdFire family
 	 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
 	 * also move to the new location.
 	 */
-	if (CONFIG_SYS_CS0_BASE != 0)
-		setvbr(CONFIG_SYS_CS0_BASE);
+	if (CFG_SYS_CS0_BASE != 0)
+		setvbr(CFG_SYS_CS0_BASE);
 #endif
 
 	icache_enable();
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index aea8f30..a083c3d 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -27,10 +27,10 @@
 
 #if defined(CONFIG_SERIAL_BOOT)
 #define ASM_DRAMINIT	(asm_dram_init - CONFIG_TEXT_BASE + \
-	CONFIG_SYS_INIT_RAM_ADDR)
+	CFG_SYS_INIT_RAM_ADDR)
 #define ASM_DRAMINIT_N	(asm_dram_init - CONFIG_TEXT_BASE)
 #define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
-	CONFIG_SYS_INIT_RAM_ADDR)
+	CFG_SYS_INIT_RAM_ADDR)
 #endif
 
 .text
@@ -123,18 +123,18 @@
 
 #ifdef CONFIG_SYS_NAND_BOOT
 	/* for assembly stack */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
 	clr.l	%sp@-
 #endif
 
 #ifdef CONFIG_CF_SBF
-	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
+	move.l	#CFG_SYS_INIT_RAM_ADDR, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
@@ -145,7 +145,7 @@
 	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
-	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -153,17 +153,17 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
 	clr.l	%sp@-
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
-	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#(CFG_SYS_CS0_BASE), (%a1)
 	move.l	#0xFC008008, %a1
-	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
-	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+	move.l	#(CFG_SYS_CS0_MASK), (%a1)
 #endif
 #endif /* CONFIG_CF_SBF */
 
@@ -216,8 +216,8 @@
 	move.l	(%a1)+, %d5
 	move.l	(%a1), %a4
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
-	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CFG_SYS_SBFHDR_SIZE), %d4
 
 	move.l	#0xFC05C02C, %a1	/* dspi status */
 
@@ -334,14 +334,14 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
-	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#(CFG_SYS_CS0_BASE), (%a1)
 	move.l	#0xFC008008, %a1
-	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
-	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+	move.l	#(CFG_SYS_CS0_MASK), (%a1)
 #endif
 
 	/* NAND port configuration */
@@ -442,10 +442,10 @@
 	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
@@ -456,7 +456,7 @@
 	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
-	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -464,7 +464,7 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 #else
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
@@ -472,7 +472,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index ceb462f..c05356f 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -135,28 +135,28 @@
 #endif				/* CONFIG_CF_V4 */
 
 
-#ifndef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_ICACR	0
+#ifndef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_ICACR	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_DCACR
-#ifdef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_DCACR	CONFIG_SYS_CACHE_ICACR
+#ifndef CFG_SYS_CACHE_DCACR
+#ifdef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_DCACR	CFG_SYS_CACHE_ICACR
 #else
-#define CONFIG_SYS_CACHE_DCACR	0
+#define CFG_SYS_CACHE_DCACR	0
 #endif
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR0
-#define CONFIG_SYS_CACHE_ACR0	0
+#ifndef CFG_SYS_CACHE_ACR0
+#define CFG_SYS_CACHE_ACR0	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR1
-#define CONFIG_SYS_CACHE_ACR1	0
+#ifndef CFG_SYS_CACHE_ACR1
+#define CFG_SYS_CACHE_ACR1	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR2
-#define CONFIG_SYS_CACHE_ACR2	0
+#ifndef CFG_SYS_CACHE_ACR2
+#define CFG_SYS_CACHE_ACR2	0
 #endif
 
 #ifndef CONFIG_SYS_CACHE_ACR3
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 672aa0b..dab8b26 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -14,7 +14,7 @@
 #include <asm/m520x.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -37,7 +37,7 @@
 #include <asm/m5235.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -59,7 +59,7 @@
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -82,7 +82,7 @@
 #include <asm/m5249.h>
 #include <asm/m5253.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -105,7 +105,7 @@
 #include <asm/m5271.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -128,7 +128,7 @@
 #include <asm/m5272.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -152,7 +152,7 @@
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(192)
@@ -175,7 +175,7 @@
 #include <asm/m5282.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
@@ -198,7 +198,7 @@
 #include <asm/m5307.h>
 
 #define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
-					(CONFIG_SYS_UART_PORT * 0x40))
+					(CFG_SYS_UART_PORT * 0x40))
 #define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS             (64)
 
@@ -223,7 +223,7 @@
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -246,7 +246,7 @@
 #include <asm/m5329.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -271,12 +271,12 @@
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 
-#if (CONFIG_SYS_UART_PORT < 4)
+#if (CFG_SYS_UART_PORT < 4)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
-					(CONFIG_SYS_UART_PORT * 0x4000))
+					(CFG_SYS_UART_PORT * 0x4000))
 #else
 #define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
-					((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+					((CFG_SYS_UART_PORT - 4) * 0x4000))
 #endif
 
 #define MMAP_DSPI			MMAP_DSPI0
@@ -320,7 +320,7 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
 
 #ifdef CONFIG_SLTTMR
 #define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
@@ -339,7 +339,7 @@
 #ifdef CONFIG_PCI
 #define CFG_SYS_PCI_BAR0		(0x40000000)
 #define CFG_SYS_PCI_BAR1		(CFG_SYS_SDRAM_BASE)
-#define CFG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR0		(CFG_SYS_MBAR)
 #define CFG_SYS_PCI_TBATR1		(CFG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M547x */
diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h
index bb12374..7c7443b 100644
--- a/arch/m68k/include/asm/immap_520x.h
+++ b/arch/m68k/include/asm/immap_520x.h
@@ -9,32 +9,32 @@
 #ifndef __IMMAP_520X__
 #define __IMMAP_520X__
 
-#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SCM1	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2	(CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0	(CFG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x000A8000)
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/edma.h>
diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h
index 27d905e..a1825c2 100644
--- a/arch/m68k/include/asm/immap_5235.h
+++ b/arch/m68k/include/asm/immap_5235.h
@@ -9,42 +9,42 @@
 #ifndef __IMMAP_5235__
 #define __IMMAP_5235__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CFG_SYS_MBAR + 0x001F0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h
index b599ca6..aa4c3ef 100644
--- a/arch/m68k/include/asm/immap_5249.h
+++ b/arch/m68k/include/asm/immap_5249.h
@@ -8,13 +8,13 @@
 #ifndef __IMMAP_5249__
 #define __IMMAP_5249__
 
-#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_INTC		(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI		(CFG_SYS_MBAR + 0x00000400)
 
 #include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/qspi.h>
diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h
index 883782a..1ab7243 100644
--- a/arch/m68k/include/asm/immap_5253.h
+++ b/arch/m68k/include/asm/immap_5253.h
@@ -9,20 +9,20 @@
 #ifndef __IMMAP_5253__
 #define __IMMAP_5253__
 
-#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_I2C0		(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_CAN0		(CONFIG_SYS_MBAR + 0x00010000)
-#define MMAP_CAN1		(CONFIG_SYS_MBAR + 0x00011000)
+#define MMAP_INTC		(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0		(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI		(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0		(CFG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1		(CFG_SYS_MBAR + 0x00011000)
 
-#define MMAP_PAR		(CONFIG_SYS_MBAR2 + 0x0000019C)
-#define MMAP_I2C1		(CONFIG_SYS_MBAR2 + 0x00000440)
-#define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
+#define MMAP_PAR		(CFG_SYS_MBAR2 + 0x0000019C)
+#define MMAP_I2C1		(CFG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CFG_SYS_MBAR2 + 0x00000C00)
 
 #include <asm/coldfire/ata.h>
 #include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h
index 27d7861..a5bf18c 100644
--- a/arch/m68k/include/asm/immap_5271.h
+++ b/arch/m68k/include/asm/immap_5271.h
@@ -9,42 +9,42 @@
 #ifndef __IMMAP_5271__
 #define __IMMAP_5271__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CFG_SYS_MBAR + 0x001F0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h
index cd7b672..c5c3cc7 100644
--- a/arch/m68k/include/asm/immap_5272.h
+++ b/arch/m68k/include/asm/immap_5272.h
@@ -8,24 +8,24 @@
 #ifndef __IMMAP_5272__
 #define __IMMAP_5272__
 
-#define MMAP_CFG	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000020)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x000000A0)
-#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x000000C0)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x000000E0)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_TMR0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_TMR1	(CONFIG_SYS_MBAR + 0x00000220)
-#define MMAP_TMR2	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_TMR3	(CONFIG_SYS_MBAR + 0x00000260)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_PLIC	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00000840)
-#define MMAP_USB	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_CFG	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CFG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM	(CFG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1	(CFG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3	(CFG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00000840)
+#define MMAP_USB	(CFG_SYS_MBAR + 0x00001000)
 
 #include <asm/coldfire/pwm.h>
 
diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h
index 8b1a08b..9b8d71d 100644
--- a/arch/m68k/include/asm/immap_5275.h
+++ b/arch/m68k/include/asm/immap_5275.h
@@ -10,44 +10,44 @@
 #ifndef __IMMAP_5275__
 #define __IMMAP_5275__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FEC0FIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00001800)
-#define MMAP_FEC1FIFO	(CONFIG_SYS_MBAR + 0x00001C00)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110004)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_USB	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1	(CFG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO	(CFG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0	(CFG_SYS_MBAR + 0x001D0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h
index d7c68f5..f810a4d 100644
--- a/arch/m68k/include/asm/immap_5282.h
+++ b/arch/m68k/include/asm/immap_5282.h
@@ -8,42 +8,42 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAMC	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_QADC	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_GPTMRA	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_GPTMRB	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_CFMC	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM	(CFG_SYS_MBAR + 0x04000000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h
index 29e6086..e1f7858 100644
--- a/arch/m68k/include/asm/immap_5301x.h
+++ b/arch/m68k/include/asm/immap_5301x.h
@@ -9,46 +9,46 @@
 #ifndef __IMMAP_5301X__
 #define __IMMAP_5301X__
 
-#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_MPU	(CONFIG_SYS_MBAR + 0x00014000)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00034000)
-#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT1	(CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_VOICOD	(CONFIG_SYS_MBAR + 0x0009C000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x000B4000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x000C4000)
-#define MMAP_IIM	(CONFIG_SYS_MBAR + 0x000C8000)
-#define MMAP_ESDHC	(CONFIG_SYS_MBAR + 0x000CC000)
+#define MMAP_SCM1	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU	(CFG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1	(CFG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2	(CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0	(CFG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1	(CFG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD	(CFG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC	(CFG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM	(CFG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG	(CFG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH	(CFG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CFG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM	(CFG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC	(CFG_SYS_MBAR + 0x000CC000)
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/dspi.h>
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
index 930e089..d6442d9 100644
--- a/arch/m68k/include/asm/immap_5307.h
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -7,15 +7,15 @@
 #ifndef __IMMAP_5307__
 #define __IMMAP_5307__
 
-#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_CSM	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DRAMC	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000244)
+#define MMAP_SIM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00000244)
 
 typedef struct sim {
 	u8  rsr;
diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h
index 9303629..afafb4e 100644
--- a/arch/m68k/include/asm/m5249.h
+++ b/arch/m68k/include/asm/m5249.h
@@ -14,14 +14,14 @@
 /*
  * useful definitions for reading/writing MBAR offset memory
  */
-#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar2_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
-#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
 
 /*
  * Size of internal RAM
diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h
index 7ebeddb..e63b42c 100644
--- a/arch/m68k/include/asm/m5271.h
+++ b/arch/m68k/include/asm/m5271.h
@@ -11,12 +11,12 @@
 #ifndef	_MCF5271_H_
 #define	_MCF5271_H_
 
-#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
-#define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_readShort(x)	*((volatile unsigned short *) (CFG_SYS_MBAR + x))
+#define mbar_readByte(x)	*((volatile unsigned char *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
 
 #define MCF_FMPLL_SYNCR				0x120000
 #define MCF_FMPLL_SYNSR				0x120004
diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h
index 0c91cf4..180f203 100644
--- a/arch/m68k/include/asm/m5282.h
+++ b/arch/m68k/include/asm/m5282.h
@@ -108,112 +108,112 @@
 
 /* General Purpose I/O Module GPIO */
 
-#define MCFGPIO_PORTA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
-#define MCFGPIO_PORTB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
-#define MCFGPIO_PORTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
-#define MCFGPIO_PORTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
-#define MCFGPIO_PORTE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
-#define MCFGPIO_PORTF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
-#define MCFGPIO_PORTG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
-#define MCFGPIO_PORTH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
-#define MCFGPIO_PORTJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
-#define MCFGPIO_PORTDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
-#define MCFGPIO_PORTEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
-#define MCFGPIO_PORTEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
-#define MCFGPIO_PORTAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
-#define MCFGPIO_PORTQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
-#define MCFGPIO_PORTSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
-#define MCFGPIO_PORTTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
-#define MCFGPIO_PORTTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
-#define MCFGPIO_PORTUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
+#define MCFGPIO_PORTA		(*(vu_char *) (CFG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CFG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CFG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CFG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CFG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CFG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CFG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CFG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_SYS_MBAR+0x100011))
 
-#define MCFGPIO_DDRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
-#define MCFGPIO_DDRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
-#define MCFGPIO_DDRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
-#define MCFGPIO_DDRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
-#define MCFGPIO_DDRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
-#define MCFGPIO_DDRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
-#define MCFGPIO_DDRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
-#define MCFGPIO_DDRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
-#define MCFGPIO_DDRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
-#define MCFGPIO_DDRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
-#define MCFGPIO_DDREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
-#define MCFGPIO_DDREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
-#define MCFGPIO_DDRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
-#define MCFGPIO_DDRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
-#define MCFGPIO_DDRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
-#define MCFGPIO_DDRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
-#define MCFGPIO_DDRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
-#define MCFGPIO_DDRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
+#define MCFGPIO_DDRA		(*(vu_char *) (CFG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CFG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CFG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CFG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CFG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CFG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CFG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CFG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CFG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CFG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_SYS_MBAR+0x100025))
 
-#define MCFGPIO_PORTAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_PORTBP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_PORTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_PORTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_PORTEP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_PORTFP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_PORTGP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_PORTHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_PORTJP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_PORTDDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_PORTEHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_PORTELP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_PORTASP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_PORTQSP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_PORTSDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_PORTTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_PORTTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_PORTUAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_SYS_MBAR+0x100039))
 
-#define MCFGPIO_SETA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_SETB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_SETC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_SETD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_SETE		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_SETF		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_SETG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_SETH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_SETJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_SETDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_SETEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_SETEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_SETAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_SETQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_SETSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_SETTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_SETTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_SETUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_SETA		(*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG		(*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH		(*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ		(*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD		(*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH		(*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL		(*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS		(*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS		(*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD		(*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC		(*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD		(*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA		(*(vu_char *) (CFG_SYS_MBAR+0x100039))
 
-#define MCFGPIO_CLRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
-#define MCFGPIO_CLRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
-#define MCFGPIO_CLRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
-#define MCFGPIO_CLRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
-#define MCFGPIO_CLRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
-#define MCFGPIO_CLRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
-#define MCFGPIO_CLRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
-#define MCFGPIO_CLRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
-#define MCFGPIO_CLRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
-#define MCFGPIO_CLRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
-#define MCFGPIO_CLREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
-#define MCFGPIO_CLREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
-#define MCFGPIO_CLRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
-#define MCFGPIO_CLRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
-#define MCFGPIO_CLRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
-#define MCFGPIO_CLRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
-#define MCFGPIO_CLRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
-#define MCFGPIO_CLRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
+#define MCFGPIO_CLRA		(*(vu_char *) (CFG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB		(*(vu_char *) (CFG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC		(*(vu_char *) (CFG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD		(*(vu_char *) (CFG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE		(*(vu_char *) (CFG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF		(*(vu_char *) (CFG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG		(*(vu_char *) (CFG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH		(*(vu_char *) (CFG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ		(*(vu_char *) (CFG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD		(*(vu_char *) (CFG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH		(*(vu_char *) (CFG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL		(*(vu_char *) (CFG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS		(*(vu_char *) (CFG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS		(*(vu_char *) (CFG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD		(*(vu_char *) (CFG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC		(*(vu_char *) (CFG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD		(*(vu_char *) (CFG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA		(*(vu_char *) (CFG_SYS_MBAR+0x10004D))
 
-#define MCFGPIO_PBCDPAR	(*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
-#define MCFGPIO_PFPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
-#define MCFGPIO_PEPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
-#define MCFGPIO_PJPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
-#define MCFGPIO_PSDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
-#define MCFGPIO_PASPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
-#define MCFGPIO_PQSPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
-#define MCFGPIO_PTCPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
+#define MCFGPIO_PBCDPAR	(*(vu_char *) (CFG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR		(*(vu_short *)(CFG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR		(*(vu_short *)(CFG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005C))
 
 /* Bit level definitions and macros */
 #define MCFGPIO_PORT7			(0x80)
@@ -310,25 +310,25 @@
 
 /* System Conrol Module SCM */
 
-#define MCFSCM_RAMBAR		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
-#define MCFSCM_CRSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
-#define MCFSCM_CWCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
-#define MCFSCM_LPICR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
-#define MCFSCM_CWSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
+#define MCFSCM_RAMBAR		(*(vu_long *) (CFG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CFG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CFG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CFG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CFG_SYS_MBAR+0x00000013))
 
-#define MCFSCM_MPARK		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
-#define MCFSCM_MPR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
-#define MCFSCM_PACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
-#define MCFSCM_PACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
-#define MCFSCM_PACR2		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
-#define MCFSCM_PACR3		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
-#define MCFSCM_PACR4		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
-#define MCFSCM_PACR5		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
-#define MCFSCM_PACR6		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
-#define MCFSCM_PACR7		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
-#define MCFSCM_PACR8		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
-#define MCFSCM_GPACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
-#define MCFSCM_GPACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
+#define MCFSCM_MPARK		(*(vu_long *) (CFG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CFG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CFG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CFG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CFG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CFG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CFG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CFG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CFG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CFG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CFG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CFG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CFG_SYS_MBAR+0x00000031))
 
 #define MCFSCM_CRSR_EXT		(0x80)
 #define MCFSCM_CRSR_CWDR	(0x20)
@@ -337,8 +337,8 @@
 
 /* Reset Controller Module RCM */
 
-#define MCFRESET_RCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
-#define MCFRESET_RSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
+#define MCFRESET_RCR		(*(vu_char *) (CFG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CFG_SYS_MBAR+0x00110001))
 
 #define MCFRESET_RCR_SOFTRST	(0x80)
 #define MCFRESET_RCR_FRCRSTOUT	(0x40)
@@ -360,9 +360,9 @@
 
 /* Chip Configuration Module CCM */
 
-#define MCFCCM_CCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
-#define MCFCCM_RCON		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
-#define MCFCCM_CIR		(*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
+#define MCFCCM_CCR		(*(vu_short *)(CFG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CFG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CFG_SYS_MBAR+0x0011000A))
 
 /* Bit level definitions and macros */
 #define MCFCCM_CCR_LOAD		(0x8000)
@@ -377,18 +377,18 @@
 
 /* Clock Module */
 
-#define MCFCLOCK_SYNCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
-#define MCFCLOCK_SYNSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
+#define MCFCLOCK_SYNCR		(*(vu_short *)(CFG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR		(*(vu_char *) (CFG_SYS_MBAR+0x120002))
 
 #define MCFCLOCK_SYNCR_MFD(x)	(((x)&0x0007)<<12)
 #define MCFCLOCK_SYNCR_RFD(x)	(((x)&0x0007)<<8)
 #define MCFCLOCK_SYNSR_LOCK	0x08
 
-#define MCFSDRAMC_DCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
-#define MCFSDRAMC_DACR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
-#define MCFSDRAMC_DMR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
-#define MCFSDRAMC_DACR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
-#define MCFSDRAMC_DMR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
+#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_SYS_MBAR+0x00000054))
 
 #define MCFSDRAMC_DCR_NAM	(0x2000)
 #define MCFSDRAMC_DCR_COC	(0x1000)
@@ -418,60 +418,60 @@
 #define MCFSDRAMC_DMR_UD	(0x00000002)
 #define MCFSDRAMC_DMR_V		(0x00000001)
 
-#define MCFWTM_WCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
-#define MCFWTM_WMR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
-#define MCFWTM_WCNTR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
-#define MCFWTM_WSR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
+#define MCFWTM_WCR		(*(vu_short *)(CFG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR		(*(vu_short *)(CFG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR		(*(vu_short *)(CFG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR		(*(vu_short *)(CFG_SYS_MBAR+0x00140006))
 
 /*********************************************************************
 * General Purpose Timer (GPT) Module
 *********************************************************************/
 
-#define MCFGPTA_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
-#define MCFGPTA_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
-#define MCFGPTA_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
-#define MCFGPTA_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
-#define MCFGPTA_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
-#define MCFGPTA_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
-#define MCFGPTA_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
-#define MCFGPTA_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
-#define MCFGPTA_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
-#define MCFGPTA_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
-#define MCFGPTA_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
-#define MCFGPTA_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
-#define MCFGPTA_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
-#define MCFGPTA_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
-#define MCFGPTA_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
-#define MCFGPTA_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
-#define MCFGPTA_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
-#define MCFGPTA_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
-#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
-#define MCFGPTA_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
-#define MCFGPTA_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
-#define MCFGPTA_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_SYS_MBAR+0x1A001E))
 
-#define MCFGPTB_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
-#define MCFGPTB_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
-#define MCFGPTB_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
-#define MCFGPTB_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
-#define MCFGPTB_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
-#define MCFGPTB_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
-#define MCFGPTB_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
-#define MCFGPTB_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
-#define MCFGPTB_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
-#define MCFGPTB_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
-#define MCFGPTB_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
-#define MCFGPTB_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
-#define MCFGPTB_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
-#define MCFGPTB_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
-#define MCFGPTB_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
-#define MCFGPTB_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
-#define MCFGPTB_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
-#define MCFGPTB_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
-#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
-#define MCFGPTB_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
-#define MCFGPTB_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
-#define MCFGPTB_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_SYS_MBAR+0x1B001E))
 
 /* Bit level definitions and macros */
 #define MCFGPT_GPTIOS_IOS3		(0x08)
@@ -556,7 +556,7 @@
 
 /* Coldfire Flash Module CFM */
 
-#define MCFCFM_MCR			(*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
+#define MCFCFM_MCR			(*(vu_short *)(CFG_SYS_MBAR+0x1D0000))
 #define MCFCFM_MCR_LOCK			(0x0400)
 #define MCFCFM_MCR_PVIE			(0x0200)
 #define MCFCFM_MCR_AEIE			(0x0100)
@@ -564,23 +564,23 @@
 #define MCFCFM_MCR_CCIE			(0x0040)
 #define MCFCFM_MCR_KEYACC		(0x0020)
 
-#define MCFCFM_CLKD			(*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
+#define MCFCFM_CLKD			(*(vu_char *)(CFG_SYS_MBAR+0x1D0002))
 
-#define MCFCFM_SEC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
+#define MCFCFM_SEC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0008))
 #define MCFCFM_SEC_KEYEN		(0x80000000)
 #define MCFCFM_SEC_SECSTAT		(0x40000000)
 
-#define MCFCFM_PROT			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
-#define MCFCFM_SACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
-#define MCFCFM_DACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
-#define MCFCFM_USTAT			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
+#define MCFCFM_PROT			(*(vu_long*) (CFG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CFG_SYS_MBAR+0x1D0020))
 #define MCFCFM_USTAT_CBEIF		0x80
 #define MCFCFM_USTAT_CCIF		0x40
 #define MCFCFM_USTAT_PVIOL		0x20
 #define MCFCFM_USTAT_ACCERR		0x10
 #define MCFCFM_USTAT_BLANK		0x04
 
-#define MCFCFM_CMD			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
+#define MCFCFM_CMD			(*(vu_char*) (CFG_SYS_MBAR+0x1D0024))
 #define MCFCFM_CMD_ERSVER		0x05
 #define MCFCFM_CMD_PGERSVER		0x06
 #define MCFCFM_CMD_PGM			0x20
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 7eca672..0b4629f 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -16,7 +16,7 @@
 {
 	struct bd_info *bd = gd->bd;
 
-	bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+	bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */
 
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
@@ -38,7 +38,7 @@
 	struct bd_info *bd = gd->bd;
 
 	bdinfo_print_mhz("busfreq", bd->bi_busfreq);
-#if defined(CONFIG_SYS_MBAR)
+#if defined(CFG_SYS_MBAR)
 	bdinfo_print_num_l("mbar", bd->bi_mbar_base);
 #endif
 	bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index aa2b93e..4ddda69 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -34,18 +34,18 @@
 	*cf_icache_status = 1;
 
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
 	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
 #if defined(CONFIG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
 	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
 #endif
 #else
-	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
-	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
 #endif
 
-	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR));
 }
 
 void icache_disable(void)
@@ -72,9 +72,9 @@
 {
 	u32 temp;
 
-	temp = CONFIG_SYS_ICACHE_INV;
+	temp = CFG_SYS_ICACHE_INV;
 	if (*cf_icache_status)
-		temp |= CONFIG_SYS_CACHE_ICACR;
+		temp |= CFG_SYS_CACHE_ICACR;
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 }
@@ -89,15 +89,15 @@
 	*cf_dcache_status = 1;
 
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
-	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
 #if defined(CONFIG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
 	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
 #endif
 #endif
 
-	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR));
 }
 
 void dcache_disable(void)
@@ -124,11 +124,11 @@
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 	u32 temp;
 
-	temp = CONFIG_SYS_DCACHE_INV;
+	temp = CFG_SYS_DCACHE_INV;
 	if (*cf_dcache_status)
-		temp |= CONFIG_SYS_CACHE_DCACR;
+		temp |= CFG_SYS_CACHE_DCACR;
 	if (*cf_icache_status)
-		temp |= CONFIG_SYS_CACHE_ICACR;
+		temp |= CFG_SYS_CACHE_ICACR;
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 #endif
diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S
index 6b9f253..7063f32 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/start.S
+++ b/arch/mips/mach-mtmips/mt7621/spl/start.S
@@ -19,7 +19,7 @@
 
 #ifndef CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + \
-				CONFIG_SYS_INIT_SP_OFFSET)
+				CFG_SYS_INIT_SP_OFFSET)
 #endif
 
 #define SP_ADDR_TEMP		0xbe10dff0
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 33835ee..63c2729 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -77,10 +77,10 @@
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		SCCR_TSECCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 		SCCR_TSEC1CM |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 		SCCR_TSEC2CM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
@@ -92,10 +92,10 @@
 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 		SCCR_USBMPHCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 		SCCR_USBDRCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
 		SCCR_SATACM |
 #endif
 		0;
@@ -115,11 +115,11 @@
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
-		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		(CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
-		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
@@ -130,11 +130,11 @@
 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
-		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		(CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
-		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		(CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 #endif
 		0;
 
@@ -175,26 +175,26 @@
 	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 
 	/* System General Purpose Register */
-#ifdef CONFIG_SYS_SICRH
+#ifdef CFG_SYS_SICRH
 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
-	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
 		     &im->sysconf.sicrh);
 #else
-	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
+	__raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
 #endif
 #endif
-#ifdef CONFIG_SYS_SICRL
-	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
+#ifdef CFG_SYS_SICRL
+	__raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
-#ifdef CONFIG_SYS_GPR1
-	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#ifdef CFG_SYS_GPR1
+	__raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
 #endif
-#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
-	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
+#ifdef CFG_SYS_DDRCDR /* DDR control driver register */
+	__raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 #endif
-#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
-	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
+#ifdef CFG_SYS_OBIR /* Output buffer impedance register */
+	__raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
 #endif
 
 #if !defined(CONFIG_PINCTRL)
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 6d1c6b0..4f982b8 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -59,9 +59,9 @@
 
 	printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
-#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
 	puts("\nSDRAM: ");
-	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+	print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
 #endif
 }
 
@@ -204,12 +204,12 @@
 		return 0;
 	}
 
-#ifdef CONFIG_SYS_DDRCDR_VALUE
+#ifdef CFG_SYS_DDRCDR_VALUE
 	/*
 	 * Adjust DDR II IO voltage biasing.  It just makes it work.
 	 */
 	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
-		immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+		immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
 	}
 	udelay(50000);
 #endif
@@ -693,7 +693,7 @@
 		ddr->sdram_mode =
 			(0
 			 | (1 << (16 + 10))             /* DQS Differential disable */
-#ifdef CONFIG_SYS_DDR_MODE_WEAK
+#ifdef CFG_SYS_DDR_MODE_WEAK
 			 | (1 << (16 + 1))		/* weak driver (~60%) */
 #endif
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
@@ -767,8 +767,8 @@
 		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
 	}
 
-#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
+	ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
 #endif
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 8fcf208..7cc0383 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -54,12 +54,12 @@
 	im->sysconf.spcr |= SPCR_TBEN;
 
 	/* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#ifdef CFG_SYS_DDRCDR
+	im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
 #endif
 	/* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
-	im->sysconf.obir = CONFIG_SYS_OBIR;
+#ifdef CFG_SYS_OBIR
+	im->sysconf.obir = CFG_SYS_OBIR;
 #endif
 
 	/*
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 8a351b9..52326f0 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -246,7 +246,7 @@
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
 
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
@@ -486,7 +486,7 @@
 #if defined(CONFIG_WATCHDOG)
 	/* Initialise the Watchdog values and reset it (if req) */
 	/*------------------------------------------------------*/
-	lis r4, CONFIG_SYS_WATCHDOG_VALUE
+	lis r4, CFG_SYS_WATCHDOG_VALUE
 	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 	stw r4, SWCRR(r3)
 
@@ -1048,10 +1048,10 @@
 lock_ram_in_cache:
 	/* Allocate Initial RAM in data cache.
 	 */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
-		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
 	dcbz	r0, r3
@@ -1070,10 +1070,10 @@
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
-		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3
 	dcbi	r0, r3
@@ -1122,14 +1122,14 @@
 	 * LBIU Local Access Widow 0 will not cover this memory space.  So, we
 	 * need another window to map in it.
 	 */
-	lis r4, (CONFIG_SYS_FLASH_BASE)@h
-	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
-	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
+	lis r4, (CFG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */
 
-	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
+	/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */
 	lis r4, (0x80000012)@h
 	ori r4, r4, (0x80000012)@l
-	li r5, CONFIG_SYS_FLASH_SIZE
+	li r5, CFG_SYS_FLASH_SIZE
 1:	srawi. r5, r5, 1	/* r5 = r5 >> 1 */
 	addi r4, r4, 1
 	bne 1b
@@ -1150,24 +1150,24 @@
 	lwz r4, BR0(r3)
 	li  r5, 0x7FFF
 	and r4, r4, r5
-	lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
-	ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
+	lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h
+	ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l
 	or  r5, r5, r4
-	stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+	stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
 
 	lwz r4, OR0(r3)
-	lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
+	lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1)
 	or r4, r4, r5
 	stw r4, OR0(r3)
 
-	lis r4, (CONFIG_SYS_FLASH_BASE)@h
-	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
-	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
+	lis r4, (CFG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */
 
-	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
+	/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */
 	lis r4, (0x80000012)@h
 	ori r4, r4, (0x80000012)@l
-	li r5, CONFIG_SYS_FLASH_SIZE
+	li r5, CFG_SYS_FLASH_SIZE
 1:	srawi. r5, r5, 1 /* r5 = r5 >> 1 */
 	addi r4, r4, 1
 	bne 1b
diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
index f8c2f10..b2f9807 100644
--- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
+++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
@@ -1,7 +1,7 @@
 #ifdef CONFIG_ARCH_MPC8308
 
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (\
+#ifndef CFG_SYS_SICRL
+#define CFG_SYS_SICRL (\
 	CONFIG_SICRL_SPI |\
 	CONFIG_SICRL_UART |\
 	CONFIG_SICRL_IRQ |\
@@ -10,8 +10,8 @@
 )
 #endif
 
-#ifndef CONFIG_SYS_SICRH
-#define CONFIG_SYS_SICRH (\
+#ifndef CFG_SYS_SICRH
+#define CFG_SYS_SICRH (\
 	CONFIG_SICRH_ESDHC_A |\
 	CONFIG_SICRH_ESDHC_B |\
 	CONFIG_SICRH_ESDHC_C |\
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 3dccc0e..013a171 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ed89011..c7d473d 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -23,7 +23,7 @@
  */
 static void check_erratum_a4849(uint32_t svr)
 {
-	void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
+	void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
 	unsigned int i;
 
 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
@@ -120,7 +120,7 @@
  */
 static void check_erratum_a007212(void)
 {
-	u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+	u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
 
 	if (in_be32(plldgdcr) & 0x1fe) {
 		/* check if PLL ratio is set by workaround */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6acd31d..74ad748 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -417,7 +417,7 @@
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
-	!defined(CONFIG_SYS_INIT_L2_ADDR)
+	!defined(CFG_SYS_INIT_L2_ADDR)
 int dram_init(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
@@ -486,7 +486,7 @@
 #endif /* CONFIG_SYS_RAMBOOT */
 #endif
 
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CONFIG_POST & CFG_SYS_POST_MEMORY
 
 /* Board-specific functions defined in each board's ddr.c */
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
@@ -591,7 +591,7 @@
 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 {
-	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
 	unsigned long epn;
 	u32 tsize, valid, ptr;
 	int ddr_esel;
@@ -624,8 +624,8 @@
 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 
 #if !defined(CONFIG_PHYS_64BIT) || \
-    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
-	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 		test_cap = p_size;
 #else
 		test_cap = gd->ram_size;
@@ -635,7 +635,7 @@
 		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
 		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 			return -1;
-		*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+		*vstart = CFG_SYS_DDR_SDRAM_BASE;
 		*size = (u32) p_size;
 		printf("Testing 0x%08llx - 0x%08llx\n",
 			(u64)(*vstart) + (*phys_offset),
@@ -651,13 +651,13 @@
 {
 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 
-	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	*vstart = CFG_SYS_DDR_SDRAM_BASE;
 	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
 	*phys_offset = 0;
 
 #if !defined(CONFIG_PHYS_64BIT) || \
-    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
-	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 			puts("Cannot test more than ");
 			print_size(CONFIG_MAX_MEM_MAPPED,
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c320b2..f07e8ab 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -165,7 +165,7 @@
 	for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 			/* find and disable LAW of SRAM */
-			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+			struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
 
 			if (law.index == -1) {
 				printf("\nFatal error happened\n");
@@ -315,15 +315,15 @@
 {
 	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 ddr_pll_ratio;
-	u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
-	u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
-	u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+	u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
+	u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
+	u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
-	u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
-	u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+	u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
+	u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
-	u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
-	u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+	u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
+	u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
 #endif
 #endif
 	/*
@@ -378,7 +378,7 @@
 ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
@@ -403,7 +403,7 @@
 
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	/* Disable the LAW created for NOR flash by the PBI commands */
-	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+	law = find_law(CFG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
 		disable_law(law.index);
 
@@ -430,7 +430,7 @@
 	/* Invalidate the CPC before DDR gets enabled */
 	invalidate_cpc();
 
- #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ #ifdef CFG_SYS_DCSRBAR_PHYS
 	/* set DCSRCR so that DCSR space is 1G */
 	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 	in_be32(&gur->dcsrcr);
@@ -533,7 +533,7 @@
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
 	if (cache_ctl & MPC85xx_L2CTL_L2E) {
 		/* Clear L2 SRAM memory-mapped base address */
 		out_be32(&l2cache->l2srbar0, 0x0);
@@ -590,15 +590,15 @@
 
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
-#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
 		u32 l2srbar = l2cache->l2srbar0;
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
-				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
-			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
+				&& l2srbar >= CFG_SYS_FLASH_BASE) {
+			l2srbar = CFG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
-			printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+			printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
 		}
-#endif /* CONFIG_SYS_INIT_L2_ADDR */
+#endif /* CFG_SYS_INIT_L2_ADDR */
 		puts("\n");
 	} else {
 		asm("msync;isync");
@@ -625,9 +625,9 @@
 #endif
 
 	/* enable the cache */
-	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+	mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
 
-	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+	if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 			;
 		print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
@@ -656,7 +656,7 @@
 int cpu_init_r(void)
 {
 	__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
 	fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -763,13 +763,13 @@
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 	if (IS_SVR_REV(svr, 1, 0)) {
 		int i;
-		__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+		__be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
 
 		for (i = 0; i < 12; i++) {
 			p += i + (i > 5 ? 11 : 0);
 			out_be32(p, 0x2);
 		}
-		p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+		p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
 		out_be32(p, 0x34);
 	}
 #endif
@@ -799,18 +799,18 @@
 	{
 		if (SVR_MAJ(svr) < 3) {
 			void *p;
-			p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+			p = (void *)CFG_SYS_DCSRBAR + 0x20520;
 			setbits_be32(p, 1 << (31 - 14));
 		}
 	}
 #endif
 
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing
 	 * speed for NOR flash.
 	 */
-	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
@@ -850,7 +850,7 @@
 	 */
 	if (IS_SVR_REV(get_svr(), 1, 0)) {
 		struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
-			(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+			(CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
 		setbits_be32(&dcfg->ecccr1,
 				(DCSR_DCFG_ECC_DISABLE_USB1 |
 				 DCSR_DCFG_ECC_DISABLE_USB2));
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 18bfa2a..a67f37e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -17,15 +17,15 @@
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
-	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
+	phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
 
 	/*
 	 * Adjust the TLB we were running out of to match the phys addr of the
 	 * chip select we are adjusting and will return to.
 	 */
-	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+	flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
 
 	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
@@ -52,7 +52,7 @@
  *
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's physical address is going to change as
- * CONFIG_SYS_FLASH_BASE_PHYS.
+ * CFG_SYS_FLASH_BASE_PHYS.
  */
 	_mas0 = MAS0_TLBSEL(1) |
 			MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
@@ -72,9 +72,9 @@
 #endif
 
 	/* Change flash's physical address */
-	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
 
 	return;
 }
@@ -101,7 +101,7 @@
 
 #ifdef CONFIG_ARCH_QEMU_E500
 	/*
-	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+	 * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
 	 * so we need to populate it before it accesses it.
 	 */
 	gd->fdt_blob = fdt;
@@ -109,9 +109,9 @@
 
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
-	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
-	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
-	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+	mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+	mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
 
 	write_tlb(mas0, mas1, mas2, mas3, mas7);
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 32348b4..a7e1df1 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -144,14 +144,14 @@
 	}
 #ifdef CONFIG_DEEP_SLEEP
 #ifdef CONFIG_SPL_MMC_BOOT
-	off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
-		CONFIG_SYS_MMC_U_BOOT_SIZE);
+	off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START,
+		CFG_SYS_MMC_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SD deep sleep: %s\n",
 		       fdt_strerror(off));
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
-		CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+	off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START,
+		CFG_SYS_SPI_FLASH_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SPI deep sleep: %s\n",
 		       fdt_strerror(off));
@@ -448,7 +448,7 @@
 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 			  unsigned long freq)
 {
-	phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+	phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS;
 	int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 
 	if (off >= 0) {
@@ -679,17 +679,17 @@
 
 	ft_fixup_dpaa_clks(blob);
 
-#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+#if defined(CFG_SYS_BMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,bman-portal", "bman-portals",
-			(u64)CONFIG_SYS_BMAN_MEM_PHYS,
-			CONFIG_SYS_BMAN_MEM_SIZE);
+			(u64)CFG_SYS_BMAN_MEM_PHYS,
+			CFG_SYS_BMAN_MEM_SIZE);
 	fdt_fixup_bportals(blob);
 #endif
 
-#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+#if defined(CFG_SYS_QMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,qman-portal", "qman-portals",
-			(u64)CONFIG_SYS_QMAN_MEM_PHYS,
-			CONFIG_SYS_QMAN_MEM_SIZE);
+			(u64)CFG_SYS_QMAN_MEM_PHYS,
+			CFG_SYS_QMAN_MEM_SIZE);
 
 	fdt_fixup_qportals(blob);
 #endif
@@ -737,7 +737,7 @@
  * beginning of CCSR.
  */
 #define CCSR_VIRT_TO_PHYS(x) \
-	(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+	(CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
 
 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
 {
@@ -783,8 +783,8 @@
 		return 0;
 	}
 
-	if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
-		msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
+	if (addr != CFG_SYS_CCSRBAR_PHYS) {
+		msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr);
 		/* No point in checking anything else */
 		return 0;
 	}
@@ -818,12 +818,12 @@
 	 * the 'reg' property to be wrong, so check it here.  For now, we
 	 * only check for "fsl,elbc" nodes.
 	 */
-#ifdef CONFIG_SYS_LBC_ADDR
+#ifdef CFG_SYS_LBC_ADDR
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 	if (off > 0) {
 		const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 		if (reg) {
-			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
 
 			addr = fdt_translate_address(fdt, off, reg);
 			if (uaddr != addr) {
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 3a6ce32..9b6577e 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -203,7 +203,7 @@
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 	struct ccsr_sfp_regs  __iomem *sfp_regs =
-			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+			(struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR);
 	u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
 	u32 bc_status, fc_status, dc_status, pll_sr2;
 	serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 437ecde..7c2de02 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -264,9 +264,9 @@
 }
 #endif
 
-#ifndef CONFIG_SYS_DCSRBAR_PHYS
-#define CONFIG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
-#define CONFIG_SYS_DCSRBAR	0x80000000
+#ifndef CFG_SYS_DCSRBAR_PHYS
+#define CFG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
+#define CFG_SYS_DCSRBAR	0x80000000
 #define __DCSR_NOT_DEFINED_BY_CONFIG
 #endif
 
@@ -315,16 +315,16 @@
 	 */
 	{
 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
-		struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
+		struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS);
 		int law_index;
 		if (law.index == -1)
-			law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
+			law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS,
 						 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
 		else
-			set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
+			set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
 				LAW_TRGT_IF_DCSR);
 #endif
-		u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
+		u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
 		out_be32(p, rcw5);
 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 		if (law.index == -1)
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 2b79086..540a6e6 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1,  2,  1, 0),
 	SET_QP_INFO(3,  4,  2, 1),
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index 7db05d9..8f64525 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1,  2,  1, 0),
 	SET_QP_INFO(3,  4,  2, 1),
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index ba54b03..db41116 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO( 1,  2,  1, 0),
 	SET_QP_INFO( 3,  4,  2, 1),
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index 6f11c81..bd05eae 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 2, 1, 0),
 	SET_QP_INFO(3, 4, 2, 1),
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index d37e1cc..391751c 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -276,8 +276,8 @@
 	mtspr	SPRN_L2CSR1,r3
 #endif
 
-	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
-	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+	lis	r3,CFG_SYS_INIT_L2CSR0@h
+	ori	r3,r3,CFG_SYS_INIT_L2CSR0@l
 	mtspr	SPRN_L2CSR0,r3
 	isync
 2:
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e2bdc2f..a6e352c 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -218,22 +218,22 @@
 #ifndef CONFIG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
 		break;
 	case 2:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4;
 		break;
 	case 6:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown PME clock select!\n");
@@ -243,7 +243,7 @@
 
 	}
 #else
-	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+	sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
 
 #endif
 #endif
@@ -380,25 +380,25 @@
 #ifndef CONFIG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
 		break;
 	case 2:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
@@ -407,31 +407,31 @@
 		break;
 	}
 #if (CFG_SYS_NUM_FMAN) == 2
-#ifdef CONFIG_SYS_FM2_CLK
+#ifdef CFG_SYS_FM2_CLK
 #define FM2_CLK_SEL	0x00000038
 #define FM2_CLK_SHIFT	3
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1];
 		break;
 	case 2:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[1] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan2 clock select!\n");
@@ -442,7 +442,7 @@
 #endif
 #endif	/* CFG_SYS_NUM_FMAN == 2 */
 #else
-	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
+	sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK;
 #endif
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 47df3c2..ce2b9c2 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -14,10 +14,10 @@
 
 ulong cpu_init_f(void)
 {
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 
-	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+	out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
 
 	/* set MBECCDIS=1, SBECCDIS=1 */
 	out_be32(&l2cache->l2errdis,
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5341756..562b699 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -128,7 +128,7 @@
 	.Lconf_pair_start:
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
-	.long CONFIG_SYS_INIT_L2_ADDR
+	.long CFG_SYS_INIT_L2_ADDR
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
 	.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
@@ -428,12 +428,12 @@
 	mtspr	SPRN_BUCSR,r0
 #endif
 
-#if defined(CONFIG_SYS_INIT_DBCR)
+#if defined(CFG_SYS_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
 	mtspr	DBSR,r1			/* Clear all status bits */
-	lis	r0,CONFIG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
-	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
+	lis	r0,CFG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
+	ori	r0,r0,CFG_SYS_INIT_DBCR@l
 	mtspr	DBCR0,r0
 #endif
 
@@ -573,34 +573,34 @@
  * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  * long-term TLBs, so we use TLB0 here.
  */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS)
 
-#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
-#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
+#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW)
+#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined."
 #endif
 
 create_ccsr_new_tlb:
 	/*
 	 * Create a TLB for the new location of CCSR.  Register R8 is reserved
-	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
+	 * for the virtual address of this TLB (CFG_SYS_CCSRBAR).
 	 */
-	lis	r8, CONFIG_SYS_CCSRBAR@h
-	ori	r8, r8, CONFIG_SYS_CCSRBAR@l
-	lis	r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
-	ori	r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
+	lis	r8, CFG_SYS_CCSRBAR@h
+	ori	r8, r8, CFG_SYS_CCSRBAR@l
+	lis	r9, (CFG_SYS_CCSRBAR + 0x1000)@h
+	ori	r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l
 	create_tlb0_entry 0, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
-		CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+		CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+		CFG_SYS_CCSRBAR_PHYS_HIGH, r3
 	/*
 	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
-	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
+	 * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
 	create_tlb0_entry 1, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
 		0, r3 /* The default CCSR address is always a 32-bit number */
 
@@ -634,7 +634,7 @@
 
 #ifdef CONFIG_FSL_CORENET
 
-#define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
+#define CCSR_LAWBARH0	(CFG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_4K	0xb
 #define CCSRBAR_LAWAR	(LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
 #define CCSRAR_C	0x80000000	/* Commit */
@@ -644,10 +644,10 @@
 	 * On CoreNet systems, we create the temporary LAW using a special LAW
 	 * target ID of 0x1e.  LAWBARH is at offset 0xc00 in CCSR.
 	 */
-	lis     r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori     r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	lis     r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
-	ori     r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis     r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori     r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis     r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+	ori     r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
 	lis     r2, CCSRBAR_LAWAR@h
 	ori     r2, r2, CCSRBAR_LAWAR@l
 
@@ -683,10 +683,10 @@
 	 * instruction.
 	 */
 write_new_ccsrbar:
-	lis	r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	lis	r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
-	ori	r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis	r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis	r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+	ori	r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
 	lis	r2, CCSRAR_C@h
 	ori	r2, r2, CCSRAR_C@l
 
@@ -723,9 +723,9 @@
 	lwz	r0, 0(r9)
 	isync
 
-/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
-#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
-			   (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
+/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */
+#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
+			   (CFG_SYS_CCSRBAR_PHYS_LOW >> 12))
 
 	/* Write the new value to CCSRBAR. */
 	lis	r0, CCSRBAR_PHYS_RS12@h
@@ -752,10 +752,10 @@
 
 	/* Delete the temporary TLBs */
 delete_temp_tlbs:
-	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
-	delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
 
-#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */
 
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 create_ccsr_l2_tlb:
@@ -765,14 +765,14 @@
 	 */
 	create_tlb0_entry 0, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+		CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+		CFG_SYS_CCSRBAR_PHYS_HIGH, r3
 
 enable_l2_cluster_l2:
 	/* enable L2 cache */
-	lis	r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
-	ori	r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+	lis	r3, (CFG_SYS_CCSRBAR + 0xC20000)@h
+	ori	r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l
 	li	r4, 33	/* stash id */
 	stw	r4, 4(r3)
 	lis	r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -813,7 +813,7 @@
 	beq	1b
 
 delete_ccsr_l2_tlb:
-	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
 
 	/*
@@ -863,7 +863,7 @@
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
-#define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
+#define DCSR_LAWBARH0	(CFG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
 #define DCSRBAR_LAWAR	(LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
 
@@ -884,13 +884,13 @@
 	rlwimi	r0, r8, 16, MAS0_ESEL_MSK
 	lis	r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
 	ori	r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
-	lis	r7, CONFIG_SYS_CCSRBAR@h
-	ori	r7, r7, CONFIG_SYS_CCSRBAR@l
+	lis	r7, CFG_SYS_CCSRBAR@h
+	ori	r7, r7, CFG_SYS_CCSRBAR@l
 	ori	r2, r7, MAS2_I|MAS2_G
-	lis	r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
-	ori	r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-	lis	r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis	r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
+	ori	r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+	lis	r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l
 	mtspr	MAS0, r0
 	mtspr	MAS1, r1
 	mtspr	MAS2, r2
@@ -1132,7 +1132,7 @@
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
 /*
@@ -1148,7 +1148,7 @@
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
 #else
@@ -1164,19 +1164,19 @@
 #endif
 
 	/* create a temp mapping in AS=1 to the stack */
-#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
-    defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
+#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
+    defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
 	create_tlb1_entry 14, \
 		1, BOOKE_PAGESZ_16K, \
-		CONFIG_SYS_INIT_RAM_ADDR, 0, \
-		CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+		CFG_SYS_INIT_RAM_ADDR, 0, \
+		CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
 
 #else
 	create_tlb1_entry 14, \
 		1, BOOKE_PAGESZ_16K, \
-		CONFIG_SYS_INIT_RAM_ADDR, 0, \
-		CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_RAM_ADDR, 0, \
+		CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #endif
 
@@ -1194,8 +1194,8 @@
 
 	/* Allocate Initial RAM in data cache.
 	 */
-	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	lis	r3,CFG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_SYS_INIT_RAM_ADDR@l
 	mfspr	r2, L1CFG0
 	andi.	r2, r2, 0x1ff
 	/* cache size * 1024 / (2 * L1 line size) */
@@ -1230,11 +1230,11 @@
 	.globl	_start_cont
 _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
-	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
-	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+	lis	r3,(CFG_SYS_INIT_RAM_ADDR)@h
+	ori	r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
@@ -1243,8 +1243,8 @@
 #endif
 
 	/* End of RAM */
-	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
-	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+	lis	r4,(CFG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l
 
 	li	r0,0
 
@@ -1826,8 +1826,8 @@
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
-	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
-	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
+	lis	r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+	ori	r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
 	mfspr	r4,L1CFG0
 	andi.	r4,r4,0x1ff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
@@ -1844,8 +1844,8 @@
 	sync
 
 	/* Invalidate the TLB entries for the cache */
-	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	lis	r3,CFG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_SYS_INIT_RAM_ADDR@l
 	tlbivax	0,r3
 	addi	r3,r3,0x1000
 	tlbivax	0,r3
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
index d2744bb..bab076b 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 99b52ba..59f4f9c 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
index 17521dc..390bb11 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index 8fe4e96..37ea778 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 81e6072..5d21bef 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -302,7 +302,7 @@
 unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
 				 unsigned int memsize_in_meg)
 {
-	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE;
 	u64 memsize = (u64)memsize_in_meg << 20;
 	u64 size;
 
@@ -324,13 +324,13 @@
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
 	return
-		setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+		setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 }
 
 /* Invalidate the DDR TLBs for the requested size */
 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
-	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
 	unsigned long epn;
 	u32 tsize, valid, ptr;
 	phys_addr_t rpn = 0;
@@ -351,7 +351,7 @@
 
 void clear_ddr_tlbs(unsigned int memsize_in_meg)
 {
-	clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+	clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 }
 
 
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f28826c..d918b43 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -64,7 +64,7 @@
 	_end = .;
 
 #if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
 	mmc_u_boot_offs = .;
 #endif
 #endif
@@ -101,7 +101,7 @@
 	.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
 	mmc_u_boot_offs = .;
 #endif
 #endif
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 0ebb7b3..1f1107e 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -141,8 +141,8 @@
 	mtspr	DER, r2
 
 	/* set up the stack on top of internal DPRAM */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l
 	stw	r0, -4(r3)
 	stw	r0, -8(r3)
 	addi	r1, r3, -8
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 1101b91..1c051d1 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -230,7 +230,7 @@
 
 int pamu_init(void)
 {
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	struct ccsr_pamu *regs;
 	u32 i = 0;
 	u64 ppaact_phys, ppaact_lim, ppaact_size;
@@ -292,7 +292,7 @@
 void pamu_enable(void)
 {
 	u32 i = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
 		setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
 			     PAMU_PCR_PE);
@@ -304,7 +304,7 @@
 void pamu_reset(void)
 {
 	u32 i  = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	struct ccsr_pamu *regs;
 
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
@@ -328,7 +328,7 @@
 void pamu_disable(void)
 {
 	u32 i  = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 
 
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
index 71496ab..caad667 100644
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -21,17 +21,17 @@
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
 	i++;
-#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+#ifdef CFG_SYS_FLASH_BASE_PHYS
 	tbl->start_addr[i] =
-		(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+		(uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS);
 	tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
 	i++;
 #endif
-#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
+#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
 	tbl->start_addr[i] =
-		(uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
+		(uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR);
 	tbl->size[i] = 256 * 1024; /* 256K CPC flash */
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 2edf0d6..d9e5a7d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -43,9 +43,9 @@
 #elif defined(CONFIG_ARCH_P1023)
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	2
-#define CONFIG_SYS_QMAN_NUM_PORTALS	3
-#define CONFIG_SYS_BMAN_NUM_PORTALS	3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x10000
+#define CFG_SYS_QMAN_NUM_PORTALS	3
+#define CFG_SYS_BMAN_NUM_PORTALS	3
+#define CFG_SYS_FM_MURAM_SIZE	0x10000
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_ARCH_P1024)
@@ -68,7 +68,7 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -78,7 +78,7 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -90,7 +90,7 @@
 #define CFG_SYS_NUM_FM2_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	1
 #define CFG_SYS_NUM_FM2_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -103,7 +103,7 @@
 #define CFG_SYS_NUM_FM1_10GEC	1
 #define CFG_SYS_NUM_FM2_DTSEC	5
 #define CFG_SYS_NUM_FM2_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
@@ -134,11 +134,11 @@
 #define CFG_SYS_FSL_SRDS_3
 #define CFG_SYS_FSL_SRDS_4
 #define CFG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_PME_CLK		0
+#define CFG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM1_CLK		3
-#define CONFIG_SYS_FM2_CLK		3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM1_CLK		3
+#define CFG_SYS_FM2_CLK		3
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -147,9 +147,9 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_MAX_DSP_CPUS		12
@@ -173,11 +173,11 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_PME_PLAT_CLK_DIV		2
-#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_FM_PLAT_CLK_DIV	1
-#define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CFG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
@@ -191,9 +191,9 @@
 #define CFG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_QBMAN_CLK_DIV		1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
@@ -212,10 +212,10 @@
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #endif
 #define CONFIG_PME_PLAT_CLK_DIV		1
-#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 5038cb9..a03f091 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -469,7 +469,7 @@
 extern void init_early_memctl_regs(void);
 extern void upmconfig(uint upm, uint *table, uint size);
 
-#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR)
 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
 #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index de85bcf..0af3d89 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,15 +18,15 @@
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -70,22 +70,22 @@
 	{ .compat[0] = name1, \
 	  .compat[1] = name2, \
 	  .id = { idA }, .num_ids = 1, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA }, .num_ids = 1, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA, idB }, .num_ids = 2, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 3e70760..e8b2680 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -9,11 +9,11 @@
 
 #ifdef CONFIG_NXP_ESBC
 #if defined(CONFIG_FSL_CORENET)
-#define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
+#define CFG_SYS_PBI_FLASH_BASE		0xc0000000
 #else
-#define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
+#define CFG_SYS_PBI_FLASH_BASE		0xce000000
 #endif
-#define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
+#define CFG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
 #if defined(CONFIG_TARGET_T2080QDS) || \
 	defined(CONFIG_TARGET_T2080RDB) || \
@@ -21,18 +21,18 @@
 	defined(CONFIG_TARGET_T1042D4RDB) || \
 	defined(CONFIG_TARGET_T1042RDB_PI) || \
 	defined(CONFIG_ARCH_T1024)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#undef CFG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR			0xbff00000
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#ifdef CONFIG_SYS_INIT_L3_VADDR
-#define CONFIG_SYS_INIT_L3_ADDR	\
-			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+#undef CFG_SYS_INIT_L3_ADDR
+#ifdef CFG_SYS_INIT_L3_VADDR
+#define CFG_SYS_INIT_L3_ADDR	\
+			(CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
 					0xbff00000
 #else
-#define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
+#define CFG_SYS_INIT_L3_ADDR		0xbff00000
 #endif
 #endif
 
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 8e18202..19774f3 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -871,11 +871,11 @@
 #define CFG_SYS_MPC83xx_ESDHC_ADDR \
 			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
 
-#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
-#define CONFIG_SYS_TSEC1_OFFSET		0x24000
-#define CONFIG_SYS_MDIO1_OFFSET		0x24000
+#define CFG_SYS_TSEC1_OFFSET		0x24000
+#define CFG_SYS_MDIO1_OFFSET		0x24000
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 #endif				/* __IMMAP_83xx__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9ae6987..283fdf3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2445,10 +2445,10 @@
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
 /* In SFPv3, OSPR register is now at offset 0x200.
  *  * So directly mapping sfp register map to this address */
-#define CONFIG_SYS_OSPR_OFFSET                  0x200
-#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#define CFG_SYS_OSPR_OFFSET                  0x200
+#define CFG_SYS_SFP_OFFSET            (0xE8000 + CFG_SYS_OSPR_OFFSET)
 #else
-#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#define CFG_SYS_SFP_OFFSET                   0xE8000
 #endif
 #define CFG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
@@ -2489,7 +2489,7 @@
 #define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CFG_SYS_FSL_SEC_OFFSET		0x300000
 #define CFG_SYS_FSL_JR0_OFFSET		0x301000
-#define CONFIG_SYS_SEC_MON_OFFSET		0x314000
+#define CFG_SYS_SEC_MON_OFFSET		0x314000
 #define CFG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CFG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CFG_SYS_FSL_BMAN_OFFSET		0x31a000
@@ -2542,13 +2542,13 @@
 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
 #ifdef CONFIG_TSECV2
-#define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#define CFG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
-#define CONFIG_SYS_TSEC1_OFFSET			0x10000
+#define CFG_SYS_TSEC1_OFFSET			0x10000
 #else
-#define CONFIG_SYS_TSEC1_OFFSET			0x24000
+#define CFG_SYS_TSEC1_OFFSET			0x24000
 #endif
-#define CONFIG_SYS_MDIO1_OFFSET			0x24000
+#define CFG_SYS_MDIO1_OFFSET			0x24000
 #define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CFG_SYS_FSL_SEC_OFFSET		0x80000
@@ -2559,8 +2559,8 @@
 #endif
 #define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
-#define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
-#define CONFIG_SYS_SFP_OFFSET			0xE7000
+#define CFG_SYS_SEC_MON_OFFSET		0xE6000
+#define CFG_SYS_SFP_OFFSET			0xE7000
 #define CFG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CFG_SYS_FSL_BMAN_OFFSET		0x8a000
 #define CFG_SYS_FSL_FM1_OFFSET		0x100000
@@ -2574,9 +2574,9 @@
 #define CFG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CFG_SYS_FSL_CPC_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+	(CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
 #define CFG_SYS_FSL_SCFG_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+	(CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
 #define CFG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
 #define CFG_SYS_FSL_BMAN_ADDR \
@@ -2603,9 +2603,9 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CFG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
-#define CONFIG_SYS_LBC_ADDR \
+#define CFG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_IFC_ADDR \
+#define CFG_SYS_IFC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
 #define CFG_SYS_MPC85xx_ESPI_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
@@ -2659,7 +2659,7 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
 #define CFG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
-#define CONFIG_SYS_PAMU_ADDR \
+#define CFG_SYS_PAMU_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
 #define CFG_SYS_PCIE1_ADDR \
@@ -2667,14 +2667,14 @@
 #define CFG_SYS_PCIE2_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 
-#define CONFIG_SYS_SFP_ADDR  \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+#define CFG_SYS_SFP_ADDR  \
+	(CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET)
 
-#define CONFIG_SYS_SEC_MON_ADDR  \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+#define CFG_SYS_SEC_MON_ADDR  \
+	(CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 struct ccsr_cluster_l2 {
@@ -2735,7 +2735,7 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
-#define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000
+#define	CFG_SYS_DCSR_DCFG_OFFSET	0X20000
 struct dcsr_dcfg_regs {
 	u8  res_0[0x520];
 	u32 ecccr1;
diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c
index d4a6057..b638ea7 100644
--- a/arch/powerpc/lib/spl.c
+++ b/arch/powerpc/lib/spl.c
@@ -23,7 +23,7 @@
 	image_entry_arg_t image_entry =
 		(image_entry_arg_t)spl_image->entry_point;
 
-	image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ,
+	image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ,
 		    0, 0);
 }
 #endif /* CONFIG_SPL_OS_BOOT */
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index 99d8797..03c196f 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -9,7 +9,7 @@
 #include <asm/processor.h>
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
+#define CFG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CFG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
 
 #endif
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index c11101b..1eb97ac 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -144,7 +144,7 @@
 
 	/* Make sure the window is below U-Boot. */
 	assert(window + LARGE_PAGE_SIZE <
-	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE);
+	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE);
 	/* Map the page into the window and then memset the appropriate part. */
 	x86_phys_map_page(window, map_addr, 1);
 	memset((void *)(window + offset), c, size);
diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h
index 3b27f93..920b5fd 100644
--- a/arch/xtensa/include/asm/addrspace.h
+++ b/arch/xtensa/include/asm/addrspace.h
@@ -22,8 +22,8 @@
  * The actual location of memory and IO is the board property.
  */
 
-#define IOADDR(x)		(CONFIG_SYS_IO_BASE + (x))
-#define MEMADDR(x)		(CONFIG_SYS_MEMORY_BASE + (x))
+#define IOADDR(x)		(CFG_SYS_IO_BASE + (x))
+#define MEMADDR(x)		(CFG_SYS_MEMORY_BASE + (x))
 #define PHYSADDR(x)		((x) - XCHAL_VECBASE_RESET_VADDR + \
 				 XCHAL_VECBASE_RESET_PADDR)